参数资料
型号: MC92603VF
厂商: Freescale Semiconductor
文件页数: 85/126页
文件大小: 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装: 1
类型: 收发器
驱动器/接收器数: 4/4
规程: 千兆位以太网
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-MAPBGA
包装: 托盘
Management Interface (MDIO)
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-5
4.2.3
MDIO RA 2 and 3—PHY Identifier Registers
Figure 4-3 shows the format for the PHY identifier registers in the MC92603. MDIO RAs 2 and 3 are
read-only and contain a 32-bit pattern that uniquely identifies the MC92603. They provide bits 3–24 of
Freescale’s ‘organizational unique identifier’ (0x000A28), the 6 least significant bits (lsb) of the part
number and the revision level for the MC92603.
4
Remote fault
Bit 4 is initialized to zero and is set when the receiver detects a remote fault. (R, LH, SC)
3
Auto-negotiation
ability
Bit 3 reports the AN ability per register 0.12. It may be changed via register 0.12 through the
MDIO interface. (R)
2
Link status
Bit 2 is initialized to zero. It reflects whether the receiver has achieved byte synchronization.
(R)
1
Jabber detect
Bit 1 is forced to zero and may not be modified. (R)
0
Extended capability
Bit 0 is forced to one and may not be modified. The MC92603 has a specific status and
configuration register (register 17) for each channel. (R)
1 R = read only, LH = latches high, and SC = self-clearing.
Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
R
Bits 03–18 of OUI
W
Reset
0
1
0
1
0
1
0
1
0
Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3
R
Bits 19–24 of OUI
Manufacturer’s Model #
Revision
W
Reset
0
1
0
Figure 4-3. PHY Identifier Registers (MDIO RA 2 and 3)
Table 4-3. Status Register (MDIO RA 1) Field Descriptions (continued)
Bits
Name
Description1
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