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型号： MC92603VF
厂商： Freescale Semiconductor
文件页数： 70/126页
文件大小： 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装： 1
类型： 收发器
驱动器/接收器数： 4/4
规程： 千兆位以太网
电源电压： 4.5 V ~ 5.5 V
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-MAPBGA
包装： 托盘
Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
3-14
Freescale Semiconductor
3.7.1.1
GMII Operation
Ethernet GMII mode is enabled by negating the TBIE input as low and asserting the COMPAT input high.
When in this mode, the receiver should be connected to a standard Gigabit Ethernet MAC, as shown in
Table 3-9.
Initially, the receiver must attain byte alignment through the detection of four COMMA code groups with
the same alignment as explained in Section 3.5.1, “Non-Aligned Mode (BSYNC = Low).” Next, the
receiver must attain stream alignment as described and shown in Figure 36-9 of the IEEE Std. 802.3-2002
specification [4].
The RECV_x_ERR output remains high until both alignments are attained.
The receiver then searches for a Start_of_Packet code group (/S/). On detection of a Start_of_Packet, the
receiver replaces that code group with a preamble code group (0x55) and present this data on the receiver
data output REC_x_7 through RECV_x_0 as the RECV_x_DV output is raised. This is per Figures 36-7a
and 36-7b of IEEE Std. 802.3-2002 specification [4].
Data continues to be presented on the data outputs, and the RECV_x_DV output remains high until an
End_of_Packet code group (/T/) is received. At this point the RECV_x_DV output is negated low and
remains low until the next Start_of_Packet is received.
Table 3-9. GMII Connection to Standard Ethernet MAC
IEEE Std. 802.3-2002
Signal Name
Function
Direction
(Relative to
MC92603)
Port Name
GTX_CLK
Transmit clock
Input
XMIT_x_CLK
TX_EN
Transmit enable
Input
XMIT_x_ENABLE
TX_ER
Force error on transmitted byte
Input
XMIT_x_ERR
TXD<7:0>
Transmit data
Input
XMIT_x_7:0]
RX_CLK
Receive clock
Output
RECV_x_RCLK
RXD<7:0>
Receive data
Output
RECV_x_[7:0]
RX_ER
Receiver has detected an error
Output
RECV_x_ERR
RX_DV
Receiver has detected data
Output
RECV_x_DV
MDC
Management data clock
Input
MD_CLK
MDIO
Management data input/output
Bidirectional
MD_DATA
The following MAC half-duplex input must be externally pulled up/down as indicated
COL
Receiver has sensed a collision
Pull down
—
CRS
Receiver has sensed a carrier
—
The following MC92603 inputs must be externally pulled up/down as indicated
Pull up
Management interface enable
Input
MDIO_EN
Variable (PUP/PUD)
MDIO PHY address
Input
MD_ADR[4:2]
Pull down
Disable unused transmitter input
Input
XMIT_x_K
Pull down
Configuration input—put in 8-bit mode
Input
TBIE
Pull up
Configuration input—put in byte synchronized
mode
Input
BSYNC
Pull down
Configuration inputs—disable word alignment
Input
WSYNC1 and WSYNC0
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