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参数资料
型号： MC92603VF
厂商： Freescale Semiconductor
文件页数： 90/126页
文件大小： 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装： 1
类型： 收发器
驱动器/接收器数： 4/4
规程： 千兆位以太网
电源电压： 4.5 V ~ 5.5 V
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-MAPBGA
包装： 托盘
Management Interface (MDIO)
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
4-10
Freescale Semiconductor
10
rcce_reg
Initialized to the value on the RCCE input. If set, indicates that the received data clock frequency
should be at the ‘recovered’ clock rate. If reset, then receive data frequency is derived from the
‘reference’ clock. See Section 3.6.1, “Recovered Clock Timing Mode (RCCE = High)” and
Section 3.6.2, “Reference Clock Timing Mode (RCCE = Low),” for an explanation. (R/W)
9
repe_reg
Initialized to the value on the REPE input. If set, indicates that received data is to be wrapped
around to transmitter to configure as a ‘repeater.’ This is for test purposes only. For details, see
Section 5.5, “Repeater Mode,” and the explanation in this Chapter 4, “Management Interface
(MDIO).” (R/W)
8
wsync1_regl
Initialized to the value on the WSYNC1 input. If set, indicates that received data for all four
channels is to be aligned into one 32-bit word output. See Section 3.5.3, “Word
Synchronization,” for an explanation. (R/W)
7
wsync0_reg
Initialized to the value on the WSYNC0 input. If set, specifies that a ‘disparity style word sync
event’ is to be used. See Section 3.5.3, “Word Synchronization,” for details. (R/W)
6
jpack_reg
Initialized to the value on the jpack input. If set, allows ‘jumbo’ packets of data to be received
(lengthens the receive FIFO). See Section 3.7.2.4, “Data Context,” for details. (R/W)
5
adie_reg
Initialized to the value on the ADIE input. If receivers are set to ‘reference clock mode’
(rcce_reg = 0), setting, adie_reg allows code groups to be inserted/deleted to prevent
overrun/underrun. See Section 3.6.2, “Reference Clock Timing Mode (RCCE = Low),” for
details. (R/W)
4
tst_1
Initialized to the value on the TST_1 input. Used together with tst_0_reg to configure various
test modes for the MC92603. (R/W)
3
tst_0
Initialized to the value on the TST_0 input. Used together with tst_1_reg to configure various
test modes for the MC92603. (R/W)
2
lboe
Initialized to the value on the LBOE input. If set, indicates that if this channel’s transmit data is
to be digitally looped back (XCVR_x_LBE = 1), that the corresponding transmit link (XLINK_x_P
and XLINK_x_N) will be active. If LBOE is low, the link will be quiescent during loopback. (R/W)
1
use_short_
an_timer
Initialized to zero. May be set through the MDIO interface only. If set it causes the auto
negotiation timer to rollover after 2 microseconds instead of the usual 10 milliseconds. Note that
this is for use during test only. (R/W)
0
ddr
Initialized to the value on the DDR input. If set, causes the MC92603 to use a DDR interface.
See Section 2.5.1.2, “Ethernet Data Transmission Process” and Section 3.7.1.3, “Double Data
Rate Operation—RGMI and RTBI.” (R/W)
1 R/W = read and write.
Table 4-6. Permanent Configuration Control Register
Field Descriptions (continued)
Bits
Name
Description1
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