参数资料
型号: MC92603VF
厂商: Freescale Semiconductor
文件页数: 49/126页
文件大小: 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装: 1
类型: 收发器
驱动器/接收器数: 4/4
规程: 千兆位以太网
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-MAPBGA
包装: 托盘
Transmitter
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
2-7
The transmitter inputs, XMIT_x_7–XMIT_x_0, XMIT_x_K, XMIT_x_ERR, and XMIT_x_ENABLE are
ignored for the next 15 byte-times while this 16-code group sequence is transmitted.
Transmitting uncoded data in backplane applications with the reduced interface mode is shown in
Table 2-4. The transmitter functional operation is the same as discussed above, except the data is entered
on both edges of the transmitter input clock, XMIT_x_CLK.
The 8 bits of uncoded data are entered with the least significant nibble on the rising clock and the most
significant nibble on the falling clock edge.
NOTE
When operating with the reduced data interface the MC92603 input pins,
XMIT_x_7–XMIT_x_4, are unused and should be terminated low.
2.4.2
Transmitting Coded Data—10-/5-Bit Modes
This operating mode is specified when the TBIE input is high. The state of COMPAT input does not affect
the transmitter’s operation.
In this mode, 10-bit coded data may be transmitted, bypassing the internal 8B/10B encoder. The 10 bits of
data to transmit are presented on the XMIT_x_7–XMIT_x_0 inputs along with bits 9 and 8 on the
XMIT_x_ERR and XMIT_x_ENABLE inputs, respectively. The 10-bit coded data is transmitted as shown
The XMIT_x_K signal is ignored by the transmitter in the backplane 10-/5-bit modes, but, it is used by the
receiver.
Table 2-4. Transmitter Inputs for Reduced Uncoded Data—Backplane Mode
Data on Rising Edge of XMIT_x_CLK
Data on Falling Edge of XMIT_x_CLK
MC92603 Signal Name
XMIT_x_ENABLE
XMIT_x_ENABLE (XOR) XMIT_x_ERR
XMIT_x_ENABLE
XMIT_x_K
Unused
XMIT_x_K
Data bits 3–0
Data bits 7–4
XMIT_x_3/XMIT_x_0
Table 2-5. Transmitter Input States for Coded Data (TBIE = High)
XMIT_x_K
XMIT_x_ERR
XMIT_x_ENABLE
XMIT_x_7–
XMIT_x_0
Description
Used by receiver
Data bit 9
Data bit 8
Data bits 7–0
Data bits 9–0
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