收藏本站
参数资料
型号： MC92603VF
厂商： Freescale Semiconductor
文件页数： 80/126页
文件大小： 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装： 1
类型： 收发器
驱动器/接收器数： 4/4
规程： 千兆位以太网
电源电压： 4.5 V ~ 5.5 V
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-MAPBGA
包装： 托盘
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-1
Chapter 4
Management Interface (MDIO)
This chapter consists of the following sections:
Section 4.1, “MDIO Interface”
Section 4.2, “MDIO Registers”
The management data input/output (MDIO) interface as defined in Clause 22 of IEEE Std. 802.3-2002 [4]
is supported by the MC92603 Quad Gigabit Ethernet transceiver. Details for protocol and electrical
characteristics are available in the standard.
This chapter provides details on the MDIO interface signals and their associated registers. The MDIO is
accessible in all of the backplane or Ethernet compatibility operational modes.
4.1
MDIO Interface
The MC92603 chip MDIO interface consists of one enable input, five address inputs, one clock input, and
one bidirectional data signal.
Some users may wish to use the MDIO interface, and others may not. If the MDIO interface is to be used
then the MDIO enable input, MDIO_EN, must be asserted high. The MDIO interface is available whether
COMPAT is enabled or not.
On power up, the MC92603 will always assume the default configuration defined by the pins of the device.
The configuration can then be changed through the MDIO interface regardless of the application operating
mode. If MDIO is not used (MDIO_EN is low), the MC92603 will operate in the default configuration.
The MDIO interface is a multidrop serial interface and each part must have a unique PHY address. Each
channel is addressed separately in the MC92603. The base address to each transceiver must be mod 4. This
address is read from three input pins that must be externally pulled up or pulled down to furnish a unique
address for each part that is connected to a MDIO bus. These three address inputs are identified as:
MD_ADR4, MD_ADR3, and MD_ADR2.
The 2 least significant bits of the 5-bit address, MD_ADR1 and MD_ADR0, are used to uniquely identify
each MC92603 channel (00 indicates channel A, 01 = B, 10 = C, and 11 = indicates channel D).
The 2.5-MHz data interface clock, MD_CLK, is sourced at the MDIO master (MAC) and is used by each
slave MDIO device. The MC92603 is designed as MDIO slave devices.
The MDIO data signal, MD_DATA, is a bidirectional serial signal used to read and write management data
from/to the MDIO registers.
相关PDF资料
PDF描述
MC92604VM IC ETH TXRX DUAL GIG 196-MAPBGA
MC92604ZT IC TXRX ETH DUAL GIG 196-MAPBGA
MCP2120T-I/SL IC ENCODR/DECODR 2.5V IR 14-SOIC
MCP2122-E/P IC ENCODER/DECODER IRDA 8-DIP
MCP2122T-E/SNG IC ENCODER/DECODR INFRARED 8SOIC
相关代理商/技术参数
参数描述
MC92603VM 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR)
MC92604VM 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR)
MC92604ZT 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件
MC92610 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES
MC92610VF 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*