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| 型号： | MC92603VF |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 58/126页 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH QUAD GIG 256-MAPBGA |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 4/4 |
| 规程： | 千兆位以太网 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-MAPBGA |
| 包装： | 托盘 |
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Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
3-3
3.2
Receiver Interface Signals
This section describes the interface signals of the MC92603 receiver. Each signal’s name, function,
direction, and active state is described in Table 3-1. The table’s signal names use the letter ‘x’ as a place
holder for the link identifier letter ‘A’ through ‘D.’ Internal signals listed in the table are not available at
the external interface of the device, but are presented to help illustrate the device’s operation.
Table 3-1. MC92603 Receiver Interface Signals
Signal Name
Description
Function
Direction
Active
State
RECV_x_[7:0]
Received byte
Receive data bits 7 through 0
Output
—
RECV_x_DV
Data valid indicator
If TBIE is high, this is the receive data, bit 8.
If TBIE is low, this is data valid indicator.
Output
—
RECV_x_K
Special data indicator
If TBIE is high, this indicates that receiver has
detected an error. The type of error is indicated in
the data byte (RECV_x_7–RECV_x_0).
If TBIE is low, this indicates whether the 8-bit
receive data is a ‘special’ code group.
Output
—
RECV_x_COMMA
COMMA indicator
This is the COMMA DETECT indicator.
RECV_x_ERR
Receiver error
If TBIE is high, this is receive data, bit 9.
If TBIE is low, see Table 3-10 and Table 3-15.
Output
—
RECV_x_RCLK
Receiver clock
Internally generated clock synchronized with
receiver data. If TBIE is high, then this clock
frequency is half of the data frequency.
Output
—
RECV_x_RCLK_B
Receiver clock complement If TBIE is high, this is the complement of
RECV_x_RCLK.
If TBIE is low, this signal is low.
Output
—
XCVR_x_DISABLE
Transceiver disable
When active receiver is disabled
Input
High
XMIT_x_K
Transmitter/receiver input
If TBIE is high, XMIT_x_K enables automatic
realignment on COMMA code groups. If XMIT_x_K
is low, initial alignment on COMMAs occurs but
subsequent realignments are disabled.
If TBIE is low, this signal is used by the transmitter
logic and ignored by the receiver logic.
Input
—
JPACK
Enable Jumbo frames
When high, this signal increases the depth of the
receive FIFO allowing longer packets of data
between bytes that may be repeated or dropped to
prevent overruns or underruns. Only needed if
RCCE is low (reference clock mode).
Input
High
RECV_REF_A
Receiver A clock enable
If RECV_REF_A and RCCE are high, then data will
be synchronized to Channel A’s recovered clock.
Input
High
WSYNC1 & WSYNC0 Word synchronization
modes
If either input is high, then all enabled receivers are
being used in unison to receive synchronized data.
Input
High
BSYNC
Byte alignment mode
Indicates that byte alignment is required. If it is low,
no byte alignment is done.
Input
—
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| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
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