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参数资料
型号： MC92603VF
厂商： Freescale Semiconductor
文件页数： 97/126页
文件大小： 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装： 1
类型： 收发器
驱动器/接收器数： 4/4
规程： 千兆位以太网
电源电压： 4.5 V ~ 5.5 V
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-MAPBGA
包装： 托盘
System Design Considerations
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
5-4
Freescale Semiconductor
5.5.2
Byte Alignment Mode
Byte alignment mode must be enabled (BSYNC = high) for repeater mode.
When establishing byte alignment for the link through the repeater, the byte alignment sequence must be
repeated twice:
Once for the repeater
Once for the destination’s receiver
At least eight IDLE code groups must be transmitted, four for the repeater’s receiver alignment and four
for the destination’s receiver alignment.
5.5.3
Word Synchronization Mode
Word synchronization may be used in repeater mode. This allows the incoming bytes to be synchronized
into their corresponding words, removing cable skew from the transmission source and re-establishing
synchronization.
Similar to byte alignment, the word synchronization sequence must be repeated twice, once for the
repeater and once for destination’s receiver. A word synchronization event must be transmitted followed
by a second word synchronization event to enable the entire link to establish word synchronization. Byte
alignment must be established, as described in Section 5.5.2, “Byte Alignment Mode,” prior to word
synchronization.
5.5.4
Recovered Clock Mode
The MC92603’s four transmitters are timed exclusively to the reference clock domain; therefore, the
recovered clock mode cannot be used in repeater mode. The setting on the recovered clock enable input,
RCCE, is ignored when in repeater mode, and all data is timed to the reference clock.
5.5.5
Add/Drop Idle Mode
Repeater mode is timed exclusively to the reference clock domain as stated above. A frequency offset
between the source transmitter and the repeater will cause the repeater’s receiver to eventually
overrun/underrun. To ensure that overrun/underrun does not cause data to be lost, ADIE must be high. The
repeater repeats or drops data from the data stream to maintain alignment to the reference clock (see
Section 3.6.2, “Reference Clock Timing Mode (RCCE = Low),” for specifics).
5.5.6
Half-Speed Mode
Half-speed mode simply affects the frequency of the reference clock that must be provided and the timing
of the receiver interface. This mode is supported in the repeater mode.
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