参数资料
型号: MC92603VF
厂商: Freescale Semiconductor
文件页数: 67/126页
文件大小: 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装: 1
类型: 收发器
驱动器/接收器数: 4/4
规程: 千兆位以太网
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-MAPBGA
包装: 托盘
Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
3-11
When word synchronization is lost it must be re-established before data flow through the receiver resumes.
The receiver interface is disabled during initial word alignment. No data is produced at its outputs until
word alignment is achieved and a word synchronization event has been detected. When establishing word
synchronization, or when word synchronization is lost, ‘not word sync’ error is reported as described in
Word synchronization is possible in byte interface mode and TBI mode. However, word synchronization
may be dependent on the detection of simultaneously transmitted word synchronization events that contain
Idle characters. Therefore, if operating in TBI mode, either the Idle character must be a supported member
of the code set or the ‘A’ character alignment must be used.
If WSE is high, then all enabled receivers (those that have XCVR_x_DISABLE negated low) will be
aligned into a 16-, 24-, or 32-bit word (depending on the states of the various XCVR_x_DISABLE
signals). If the receiver on channel A is disabled, then do not select the clock from channel A as the
recovered clock for all the channels.
3.6
Receiver Interface Timing Modes
The receiver interface is timed to the recovered clock (link partner’s clock) or to the reference clock (local
clock), depending on the state of the recovered clock enable, RCCE, signal. RCCE enables timing relative
to the recovered clock when asserted and enables timing relative to the reference clock when negated.
The receiver interface clock signals, RECV_x_RCLK, will always be present when the PLL is in lock. This
is true even if there is no signal present on the serial inputs or if the receiver has not achieved alignment
or byte sync. The frequency of the receiver clock will be the local reference clock until synchronization is
achieved. The RECV_x_RCLK clock signals, however, are not present during power up or when the
MC92603 is in reset mode and the PLL is not locked.
All receiver channels data outputs are source synchronous with their respective RECV_x_RCLK outputs.
They may be configured to be source aligned or source centered with their respective RECV_x_RCLK
outputs. The configuration signal, RECV_CLK_CENT, when asserted high, will center the receiver clocks
relative to the data and status outputs.
NOTE
The receiver clock complement, RECV_x_RCLK_B, is only provided in
the TBIE/RTBI Ethernet compliant application modes (TBIE and
COMPAT = high). If either TBIE or COMPAT is low, then
RECV_x_RCLK_B is always low.
3.6.1
Recovered Clock Timing Mode (RCCE = High)
With RCCE asserted, the receiver clock signal, RECV_x_RCLK, is generated by the receiver and, on
average, runs at the reference clock frequency of the transmitter (link partner’s clock) at the other end of
the link. The recovered clock is not generated by a clock recovery PLL but by monitoring the receive
FIFO.
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