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| 型号： | MC92603VF |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 64/126页 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH QUAD GIG 256-MAPBGA |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 4/4 |
| 规程： | 千兆位以太网 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-MAPBGA |
| 包装： | 托盘 |
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Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
3-8
Freescale Semiconductor
internal 8B/10B decoder was used to decode data from the received 10-bit character. Byte interface mode
is enabled by negating TBIE low.
Received data is 10-bits of pre-coded data when in the 10-bit interface, TBI, mode. The internal 8B/10B
decoder is not used, and it is assumed that decoding is done externally. The 10-bit interface mode is
enabled by asserting TBIE high.
The received data is presented on the interface RECV_x_7 through RECV_x_0 signals when operating in
the GMII or 8-bit backplane modes. In the 10-bit backplane or TBI modes, RECV_x_ERR, RECV_x_DV
become bits 9 and 8, respectively.
In the reduced interface operational modes, the receiver signals RECV_x_7 through RECV_x_4 are not
used and the 5th and 9th data bits are output on the RECV_x_DV signal. With the reduced interface, data
in the alignment FIFO is presented at the receiver interface as double data rate (DDR), on the rising and
falling edge of the appropriate receiver clock, RECV_x_RCLK.
The receiver status and error reporting is coded onto the RECV_x_ERR, RECV_x_DV,
RECV_x_COMMA, and RECV_x_K signals.
All of the digital outputs of the device are internally “source terminated” and therefore do not require
exernal series resistors on the pcb. This applies to all received data, status, and clock outputs on the
MC92603.
3.5
Data Alignment Configurations
The receiver supports two modes of byte alignment as defined by the BSYNC signal. Table 3-5 shows the
settings to activate each mode.
NOTE
Do not use non-aligned mode (BSYNC = low) in 8-bit modes. The
non-aligned mode is only valid if TBIE is high.
3.5.1
Non-Aligned Mode (BSYNC = Low)
In non-aligned mode no attempt is made to align the incoming data stream. The bits are simply
accumulated into 10-bit code groups and forwarded. This mode should be used only with backplane 10-
or 5-bit data mode (TBIE = high, COMPAT = low), and with word synchronization disabled
(WSYNC1 = low and WSYNC0 = low).
3.5.2
Byte-Aligned Mode (BSYNC = High)
The remaining 4 receiver operating modes, shown in Table 3-4 align the incoming serial data into 10-bit
code groups. At power up, the receiver starts an alignment procedure, searching for the 8-bit pattern
Table 3-5. Byte Synchronization Modes
Byte Alignment Mode
BSYNC
Byte Aligned
High
Non-Aligned
Low
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