参数资料
型号: MC92603VF
厂商: Freescale Semiconductor
文件页数: 87/126页
文件大小: 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装: 1
类型: 收发器
驱动器/接收器数: 4/4
规程: 千兆位以太网
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-MAPBGA
包装: 托盘
Management Interface (MDIO)
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-7
4.2.5
MDIO RA 5—Auto-Negotiation Link Partner Ability Register
Figure 4-5 shows the format for the auto-negotiation (AN) link partner register, MDIO RA 5, in the
MC92603. Register 5 is a read-only register and contains the advertised ability of the link partner.
Table 4-5 lists the corresponding field descriptions for the AN link partner ability register.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Next
Page
Acknowledge
Remote
Fault 2
Remote
Fault 1
Reserved
Pause 2 Pause 1
Half-
Duplex
Full-
Duplex
Reserved
W
Reset
0
0 0 0 0 0
Figure 4-5. AN Link Partner Ability Register (MDIO RA 5)
Table 4-5. AN Link Partner Ability Register Field Descriptions
Bits
Name
Description1
1 R = read-only.
15
Next Page
The MC92603 does not support multiple pages of configuration registers and ignores this
bit. (R)
14
Acknowledge
Ack is set when the link partner acknowledges receipt of the advertised transmitted
capabilities. (R)
13
Remote fault 2
Bits 13 and 12 are the remote status of the link partner. (R)
RF1
RF2
Interpretation
0
Link OK
12
Remote fault 1
0
1
Offline
1
0
Link_Failure
1
Auto-Negotiation_Error
11–9
Reserved
This bit is ignored
. (R)
8
Pause 1
PS1 and PS2 are pause control bits that reflect the values of bits 12 and 13 in MDIO RA 4
of the link partner. (R)
7
Pause 0
6
Half-duplex
Forced to zero. The MC92603 does not support half-duplex mode. (R)
5
Full-duplex
Forced to one. The MC92603 always runs in full-duplex mode. (R)
4–0
Reserved
This bit is ignored
. (R)
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