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参数资料
型号： MT42L64M32D1KL-3 IT:A
厂商： Micron Technology Inc
文件页数： 140/164页
文件大小： 0K
描述： IC DDR2 SDRAM 2GBIT 168FBGA
标准包装： 1,000
格式 - 存储器： RAM
存储器类型： 移动 LPDDR2 SDRAM
存储容量： 2G（64M x 32）
速度： 333MHz
接口： 并联
电源电压： 1.14 V ~ 1.3 V
工作温度： -25°C ~ 85°C
封装/外壳： 168-WFBGA
供应商设备封装： 168-FBGA（12x12）
包装： 散装
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Clock Period Jitter
t LZ(DQ), t HZ(DQ), t DQSCK, t LZ(DQS), t HZ(DQS)
These parameters are measured from a specific clock edge to a data signal transition
(DM n or DQ m , where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be
met with respect to that clock edge. Therefore, they are not affected by t JIT(per).
t QSH, t QSL
These parameters are affected by duty cycle jitter, represented by t CH(abs)min and
t CL(abs)min. These
parameters determine the absolute data valid window at the device
pin. The absolute minimum data valid window at the device pin = min [( t QSH(abs)min
× t CK(avg)min - t DQSQmax - t QHSmax), ( t QSL(abs)min × t CK(avg)min - t DQSQmax -
t QHSmax)]. This minimum data valid window must be met at the target frequency re-
gardless of clock jitter.
t RPST
t RPST
is affected by duty cycle jitter, represented by t CL(abs). Therefore, t RPST(abs)min
can be specified by t CL(abs)min. t RPST(abs)min = t CL(abs)min - 0.05 = t QSL(abs)min.
Clock Jitter Effects on WRITE Timing Parameters
t DS, t DH
These parameters are measured from a data signal (DM n or DQ m , where n = 0, 1, 2, 3;
and m = DQ[31:0]) transition edge to its respective data strobe signal (DQS n , DQS n #: n
= 0,1,2,3) crossing. The specification values are not affected by the amount of t JIT(per)
applied, because the setup and hold times are relative to the clock signal crossing that
latches the command/address. Regardless of clock jitter values, these values must be
met.
t DSS, t DSH
These parameters are measured from a data strobe signal crossing (DQS x , DQS x #) to its
clock signal crossing (CK/CK#). The specification values are not affected by the amount
of t JIT(per)) applied, because the setup and hold times are relative to the clock signal
crossing that latches the command/address. Regardless of clock jitter values, these val-
ues must be met.
t DQSS
t DQSS
is measured from the clock signal crossing (CK/CK#) to the first latching data
strobe signal crossing (DQS x , DQS x #). When the device is operated with input clock jit-
ter, this parameter must be derated by the actual t JIT(per),act of the input clock in ex-
cess of t JIT(per),allowed.
tDQSS(min,derated) = 0.75 - t JIT(per),act,min              – tJIT(per),allowed, min
tCK(avg)
tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max
tCK(avg)
For example, if the measured jitter into an LPDDR2-800 device has t CK(avg) = 2500ps,
t JIT(per),act,min = -172ps, and t JIT(per),act,max = +193ps, then:
t DQSS,(min,derated)
= 0.75 - ( t JIT(per),act,min - t JIT(per),allowed,min)/ t CK(avg) =
0.75 - (-172 + 100)/2500 = 0.7788 t CK(avg), and
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
140
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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