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R8C/38T-A Group
8. Watchdog Timer
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 78 of 730
Aug 05, 2011
8.2.1
Reset Interrupt Select Register (RISR)
Notes:
1. After reading this bit as 1, wait for at least one cycle of the count source before writing 0 to it.
2. The RIS bit is set to 1 by writing 1 by a program, but writing 0 to this bit has no effect.
When the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), the RIS bit is
automatically set to 1.
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the RISR register.
[Condition for setting to 0]
When 0 is written to this bit.
[Conditions for setting to 1]
When the watchdog timer underflows while the RIS bit is 0 (watchdog timer interrupt).
When a refresh is executed during a period other than the acceptance period (illegal refresh) while the RIS bit
is 0 (watchdog timer interrupt).
8.2.2
Watchdog Timer Reset Register (WDTR)
Note:
1. Only write to the WDTR register while the watchdog timer is counting.
Address 00020h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
1
000
0000
The above applies when the CSPROINI bit in the OFS register is 0.
After Reset
0
000
0000
The above applies when the CSPROINI bit in the OFS register is 1.
Bit
Symbol
Bit Name
Function
R/W
b0
—
Nothing is assigned. The write value must be 0. The read value is 0.
—
b1
—
b2
—
b3
—
b4
—
b5
—
b6
UFIF
WDT underflow detection flag
0: No watchdog timer underflow
1: Watchdog timer underflow
(1)R/W
b7
RIS
WDT interrupt/reset switch bit
0: Watchdog timer interrupt
1: Watchdog timer reset
(2)R/W
Address 00021h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
————
———
—
After Reset
1
111
1111
Bit
Function
R/W
b7 to b0
The watchdog timer is initialized by writing 00h and then FFh during the acceptance period.
The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUFS1 in the OFS2
W