
R8C/38T-A Group
19. Serial Interface (UART0)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 392 of 730
Aug 05, 2011
Notes:
1. The bits used are as follows:
Bits 0 to 6 when transfer data is 7 bits long
Bits 0 to 7 when transfer data is 8 bits long
Bits 0 to 8 when transfer data is 9 bits long
2. The contents of the following are undefined: Bits 7 and 8 when transfer data is 7 bits long, and bit 8 when
transfer data is 8 bits long.
Table 19.7
Registers and Settings Used in Clock Asynchronous Serial I/O Mode
Register
Bit
Function
U0TB
b0 to b8
U0RB
b0 to b8
Receive data can be read.
(2)OER
Overrun error flag
FER
Framing error flag
PER
Parity error flag
SUM
Error sum flag
U0BRG
b0 to b7
Set the bit rate.
U0MR
SMD2 to SMD0
Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Set to 110b when transfer data is 9 bits long.
CKDIR
Select an internal or external clock.
STPS
Select one or two stop bits.
PRY, PRYE
Select whether parity is enabled and whether odd or even.
U0C0
CLK0 and CLK1 Select the U0BRG count source (f1, f8, f32, or fC1).
TXEPT
Transmit register empty flag
NCH
Select the output type (CMOS or N-channel open-drain output) of the TXD pin.
CKPOL
Set to 0 (transmit data is output at the falling edge and receive data is input at the rising
edge of the transfer clock).
UFORM
Select LSB first or MSB first when transfer data is 8 bits long.
Set to 0 (LSB first) when transfer data is 7 bits or 9 bits long.
U0C1
TE
Set to 1 to enable transmission.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
U0IRS
Select the UART0 transmit interrupt source to be transmit buffer empty or transmission
complete.
U0RRM
Set to 0 (continuous receive mode disabled).