R8C/38T-A Group
22. Hardware LIN
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 527 of 730
Aug 05, 2011
22.3.1
LIN Special Function Register (LINCR2)
22.3.2
LIN Control Register (LINCT)
Notes:
1. After setting the LSTART bit, confirm that the RXDSF bit is set to 1 (RXD input disabled) before Synch Break
input starts.
2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once.
3. Inputs to timer RJ and UART are disabled immediately after the LINE bit is set to 1 (LIN operation starts). Refer
Field Reception Flowchart Examples
.
Address 0008Ch (LINCR2_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
BCE
Bus collision detection during Sync
Break transmission enable bit
0: Bus collision detection disabled
1: Bus collision detection enabled
R/W
b1
—
Nothing is assigned. The write value must be 0. The read value is 0.
—
b2
—
b3
—
b4
—
b5
—
b6
—
b7
—
Address 0008Eh (LINCT_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
SFIE
Synch Field measurement-completed
interrupt enable bit
0: Synch Field measurement-completed interrupt
disabled
1: Synch Field measurement-completed interrupt
enabled
R/W
b1
SBIE
Synch Break detection interrupt
enable bit
0: Synch Break detection interrupt disabled
1: Synch Break detection interrupt enabled
R/W
b2
BCIE
Bus collision detection interrupt
enable bit
0: Bus collision detection interrupt disabled
1: Bus collision detection interrupt enabled
R/W
b3
RXDSF
RXD input status flag
0: RXD input enabled
1: RXD input disabled
R
b4
LSTART Synch Break detection start bit
(1)When this bit is set to 1, timer RJ input is enabled
and RXD input is disabled. The read value is 0
R/W
b5
SBE
RXD input unmasking timing
select bit
(effective only in slave mode)
0: Unmasked after Synch Break detected
1: Unmasked after Synch Field measurement
completed
R/W
b6
MST
LIN operation mode set bit
(2)0: Slave mode
(Synch Break detection circuit operation)
1: Master mode (timer RJ output OR’ed with TXD)
R/W
b7
LINE
LIN operation start bit
0: LIN operation stops
1: LIN operation starts
(3)R/W