R8C/38T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 176 of 730
Aug 05, 2011
Figure 13.3
DTC Internal Operation Flowchart (i = 0 to 3, 5, or 6) (j = 0 to 23) when DTC Activation
Source is not Timer RC, Timer RE2, SSU/I2C bus, Flash Memory, or TSCU Interrupt
Source
Figure 13.4
DTC Internal Operation Flowchart (i = 0 to 3, 5, or 6) (j = 0 to 23) when DTC Activation
Source is Timer RC, Timer RE2, or TSCU Interrupt Source
DTC activation source
generation
NMIF = 1?
Read DTC vector
Read control data
Transfer data
Write back control data
CHNE = 1?
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
repeat mode
Yes
No
DTCENi0 to DTCENi7: Bits in DTCENi registers
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
Branch 1
End
No
Yes
Read control data
Transfer data
Write back control data
CHNE = 1?
No
Write 0 to the bit among
DTCENi0 to DTCENi7
Generate an interrupt request
for the CPU
Transfer data
Write back control data
CHNE = 1?
Yes
No
Interrupt handling
Read control data
Transfer data
Write back control data
CHNE = 1?
Yes
No
DTC activation source
generation
NMIF = 1?
Read DTC vector
Read control data
Write 0 to the interrupt source
flag in the status register
Transfer data
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
repeat mode
Yes
DTCENi0 to DTCENi7: Bits in DTCENi registers
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
Branch 1
No
Yes
Read control data
Transfer data
Write back control data
CHNE = 1?
No
Write 0 to the bit among
DTCENi0 to DTCENi7
Generate an interrupt request
for the CPU
Transfer data
Write back control data
CHNE = 1?
Yes
No
Interrupt handling
Read control data
Transfer data
Write back control data
CHNE = 1?
Yes
No
CHNE = 1?
No
End
Yes
Write back control data