R8C/38T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 182 of 730
Aug 05, 2011
13.3.8
Operation Timings
The DTC requires five clock cycles to read control data allocated in the DTC control data area. The number of
clock cycles required to write back control data differs depending on the control data settings.
Figure 13.11
Example of DTC Operation Timings
Figure 13.12
Example of DTC Operation Timings in Chain Transfers
j = 0 to 23
X: 0 or 1
The specifications for writing back control data in chained transfer operations depend on either normal mode or
repeat mode as listed in
Table 13.11 for each activation source, according to the operating mode set for each
activation source.
Table 13.11
Specifications of Control Data Write-Back Operation
Bits b3 to b0 in
DTCCR
Register
Operating
Mode
Address Control
Control Data to be Written Back
Number of
Clock
Cycles
Source
Destination
DTCCTj
Register
DTRLDj
Register
DTSARj
Register
DTDARj
Register
00X0b
Normal
mode
Fixed
Written back Written back
Not written
back
Not written
back
1
01X0b
Incremented
Fixed
Written back Written back Written back
Not written
back
2
10X0b
Fixed
Incremented Written back Written back
Not written
back
Written back
2
11X0b
Incremented Incremented Written back Written back Written back Written back
3
0X11b
Repeat
mode
Repeat area
Fixed
Written back Written back Written back
Not written
back
2
1X11b
Incremented Written back Written back Written back Written back
3
X001b
Fixed
Repeat area
Written back Written back
Not written
back
Written back
2
X101b
Incremented
Written back Written back Written back Written back
3
Used by CPU
Read
Write
Used by CPU
Read control data
Transfer data Write back control data
Read vector
CPU clock
Address
Used by CPU
Read
Write
Used by CPU
Read vector
Read control data
Transfer data
Write back control
data
Read control data
Transfer data Write back control data
CPU clock
Address
Read
Write