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R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 430 of 730
Aug 05, 2011
20.3.3
Special Mode 1 (I2C Mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Tables 20.9 and 20.10 list the As shown in Table 20.11, I2C mode is entered by setting bits SMD2 to SMD0 to 010b in the U2MR register and the IICM bit in the U2SMR register to 1. Because SDA2 transmit output has a delay circuit attached, SDA2
output does not change state until SCL2 goes low and stabilizes.
Table 20.9
Registers and Settings Used in I2C Mode (1)
Register
Bit
Function
Master
Slave
U2TB
b0 to b7
Set transmit data.
U2RB
b0 to b7
Receive data can be read.
b8
ACK or NACK is set in this bit.
ABT
Arbitration lost detection flag
Disabled
OER
Overrun error flag
U2BRG
b0 to b7
Set the bit rate.
Disabled
U2MR
SMD2 to SMD0
Set to 010b.
CKDIR
Set to 0.
Set to 1.
U2C0
CLK0, CLK1
Select the count source for the U2BRG
register.
Select the count source for the U2BRG
register.
CRS
Disabled
TXEPT
Transmit register empty flag
CRD
Set to 1.
NCH
Set to 1.
UFORM
Set to 1.
U2C1
TE
Set to 1 to enable transmission.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
U2IRS
Set to 1.
U2SMR
IICM
Set to 1.
ABC
Set the timing for detecting an arbitration
lost.
Disabled
BBS
Bus busy flag
U2SMR2
IICM2
CSC
Set to 1 to enable clock synchronization.
Set to 0.
SWC
Set to 1 to hold SCL2 output low at the
falling edge of the 9th bit of clock.
Set to 1 to hold SCL2 output low at the
falling edge of the 9th bit of clock.
ALS
Set to 1 to stop SDA2 output when an
arbitration lost is detected.
Set to 0.
STAC
Set to 0.
Set to 1 to initialize UART2 when a start
condition is detected.
SWC2
Set to 1 to forcibly pull SCL2 low.
Set to 1 to forcibly pull SCL2 output low.
SDHI
Set to 1 to disable SDA2 output.