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R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 514 of 730
Aug 05, 2011
21.4.4
Register Setting Examples
Figures 21.31 to 21.34 show examples of register setting when the I2C bus interface is used. Figure 21.31
Register Setting Example in Master Transmit Mode (I2C bus Interface Mode)
Start
Initial setting
Read BBSY bit in SICR2 register
End
BBSY = 0?
Write transmit data to SITDR register
Transmit
mode?
Master receive mode
TEND = 1?
No
Yes
No
(1) Determine the state of the SCL and SDA lines.
(2) Set to master transmit mode.
(3) Generate a start condition.
(4) Set the transmit data of the 1st byte (slave address + R/W).
(5) Wait until 1 byte of data is transmitted.
(6) Determine the ACKBR bit from the specified slave device.
(7) Set the transmit data after 2nd byte (except the last byte).
(8) Wait until the SITDR register is empty.
(9) Set the transmit data of the last byte.
(10) Wait for end of transmission of the last byte.
(11) Set the TEND bit to 0.
(12) Set the STOP bit to 0.
(13) Generate a stop condition.
(14) Wait until a stop condition is generated.
(15) Set to slave receive mode.
Set the TDRE bit to 0.
SICR1 register
TRS bit
1
MST bit
1
SICR2 register
SCP bit
0
BBSY bit
1
Read TEND bit in SISR register
No
Read ACKBR bit in SIER register
Yes
ACKBR = 0?
Write transmit data to SITDR register
TDRE = 1?
Read TDRE bit in SISR register
Last byte?
Write transmit data to SITDR register
TEND = 1?
Read TEND bit in SISR register
SISR register
TEND bit
0
SISR register
STOP bit
0
SICR2 register
SCP bit
0
BBSY bit
0
Read STOP bit in SISR register
STOP = 1?
SICR1 register
TRS bit
0
MST bit
0
SISR register
TDRE bit
0
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(12)
(10)
(13)
(14)
(11)
(9)
(15)
Set the STOP bit in the SISR register to 0.
Set the IICSEL bit in the IICCR register to 1.
Set the MSTIIC bit in the MSTCR1 register to 0.