R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 519 of 730
Aug 05, 2011
1 Tcyc = 1/f1 (s)
When CKS3 to CKS0 = 1000b, the bit synchronization circuit does not function even if the high-level width of
the SCL signal is 600 ns or less (a breach of the I2C specification) (when the operating clock is set to 20 MHz).
21.4.7
Coordination with DTC
■ Common to the SSU/I2C bus functions
To read the receive buffer in master mode using the DTC, set the number of transfers minus 1 in the DTC
transfer count register.
After the number of transfers minus 1 of receive data is transferred, an RXI interrupt is generated. Set the
RCVD bit in the SICR1 register to 1 (next receive operation disabled) and then set the RDRF bit in the SISR
register to 0 (no data in the SIRDR register).
If clearing of the RDRF bit is delayed and the last byte is transferred, the SCL signal is held low and a hang-up
occurs when the I2C bus function is used. When the SSU function is used, an overrun error occurs.
Setting of the RCVD bit in the SICR1 register must be performed during the receive operation of the last byte.
■ SSU Function
After the last data is received, an RXI interrupt is generated. Set the RE_STIE bit in the SIER register to 0
(reception disabled) and the RCVD bit 0 (next receive operation continues) before reading the SIRDR register
by software.
■ I2C bus Function
After the last data is received, an RXI interrupt is generated. Confirm that the SCLO bit (SCL monitor flag) in
the SICR2 register is set to 0 before generating a stop condition.
When the STOP bit in the SISR register is set to 1 (a stop condition is detected after the frame is transferred),
read the SIRDR register. Then set the RCVD bit 0 (next receive operation continues).
Table 21.12
Time between Changing SCL Signal from Low Output to High Impedance and
Monitoring SCL Signal
SICR1 Register
SCL Monitoring Time (MT)
IICTCHALF
IICTCTW1
CKS3
CKS2
00
0
7.5 Tcyc
1
19.5 Tcyc
1
0
17.5 Tcyc
1
41.5 Tcyc
01
0
2.5 Tcyc
1
8.5 Tcyc
1
0
7.5 Tcyc
1
19.5 Tcyc
10
0
17.5 Tcyc
1
41.5 Tcyc
1
0
37.5 Tcyc
1
85.5 Tcyc