R8C/38T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 185 of 730
Aug 05, 2011
13.4
Notes on DTC
13.4.1
DTC Activation Source
Do not generate any DTC activation sources before entering wait mode or during wait mode.
Do not generate any DTC activation sources before entering stop mode or during stop mode.
The DTC activation sources for the TSCU can be used for DTC transfers during wait mode.
To use a DTC activation source for the TSCU to perform DTC transfers, set the source address in the
corresponding TSCU register and the destination address in RAM in advance.
13.4.2
DTCENi Registers (i = 0 to 3, 5, or 6)
Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.
When the interrupt source flag in the status register for the peripheral function is 1, do not modify the
corresponding activation source bit among bits DTCENi0 to DTCENi7.
Do not access the DTCENi registers using DTC transfers.
13.4.3
Peripheral Modules
Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
When the DTC activation source is SSU/I2C receive data full, read the SIRDR register using a DTC transfer.
The RDRF bit in the SISR register is set to 0 (no data in the SIRDR register) by reading the SIRDR register.
However, the RDRF bit is not set to 0 by reading the SIRDR register when the DTC data transfer setting is
either of the following:
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit in the DTCCRj
register is 1 (interrupt generation enabled) in repeat mode.
When the DTC activation source is SSU/I2C transmit data empty, write to the SITDR register using a DTC
transfer. The TDRE bit in the SISR register is set to 0 (data is not transferred from registers SITDR to SISDR)
by writing to the SITDR register.
The DTC activation sources for the TSCU must be used only for DTC transfers with interrupts set to be
disabled.
13.4.4
Interrupt Requests
When the DTC activation source is either SSU/I2C transmit data empty or flash ready status, no interrupt
request is generated for the CPU in either of the following cases:
-When the DTC performs a data transfer that causes the DTCCTj register value to change to 0 in normal
mode.
-When the DTC performs a data transfer that causes the DTCCRj register value to change to 0 while the
RPTINT bit in the DTCCRj register is 1 in repeat mode.
13.4.5
DTC Activation
When the DTC is activated, operation may be shifted for one cycle before reading a vector.