R8C/38T-A Group
16. Timer RB2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 258 of 730
Aug 05, 2011
16.4
Operation
16.4.1
Timer Mode
In this mode, an internally generated count source or the timer RJ underflow is counted. Registers TRBOCR
and TRBSC are not used.
When 1 (count starts) is written to the TSTART bit in the TRBCR register, the count is started. When 0 (count
stops) is written to the TSTART bit, the count is stopped. When 1 (count is forcibly stopped) is written to the
TSTOP bit in the TRBCR register, the count is stopped.
An interrupt request is generated when the timer RB2 counter underflows.
When registers TRBPRE and TRBPR are read, each count value can be read. When registers TRBPRE and
TRBPR are written while the count is stopped, values are written to both the reload register and counter,
respectively. When these registers are written during count operation, the reload register is written. A program
can be used to select whether values are transferred to the counter at the next count operation, or written to the
reload register only and then transferred to the counter at the next reload operation.
Note:
1. The count is started after three cycles of the count source when the TSTART bit is set to 1 (count starts).
The count is stopped after three cycles of the count source when the TSTART bit is set to 0 (count stops).
Monitor the TCSTF bit in the TRBCR register to confirm the operating state of the counter.
Figure 16.2
Operation Example in Timer Mode (8-Bit Timer)
When registers TRBPR, TRBSC,
and TRBPRE are written while the
count is stopped, values are
written to both the reload register
and counter
TSTART bit in
TRBCR register
Count source
Counter input
TCSTF bit in
TRBCR register
TRBPR register
TRBPR
count register
TRBPRE
count register
TRBPRE
reload register
load signal
Interrupt request
one-shot signal
TRBPRE register
01h
02h
00h
02h
01h
00h
02h
00h
FFh
Set to 1 by a program
Synchronized with the peripheral system clock
Decrement
starts
01h
02h
Set to 0 by acknowledgment
of an interrupt request
or by a program
The above diagram applies under the following conditions:
TRBPRE register = 02h, TRBPR register = 01h
TCNT16 bit in TRBMR register = 0 (8-bit timer with 8-bit prescaler)
TOCNT bit in TRBIOC register = 0 (waveform output)
00h
02h
01h
00h
01h
Data is retained when
the count clock stops
After TRBPR is reloaded,
an interrupt is requested
TRBPR
reload register
load signal
TRBPR
is reloaded
TRBPR
is reloaded
00h
01h
00h
01h
02h
TRBPRE
is reloaded
(repeated)
TRBPRE
is reloaded
TRBPRE
is reloaded
TRBPRE
is reloaded
TRBPRE
is reloaded