R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 456 of 730
Aug 05, 2011
21.1.2
Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) supports clock synchronous serial data communication. The
SSU consists of a channel: SSU_0.
Table 21.2
Synchronous Serial Communication Unit Specifications
Item
Description
Transfer data format
Transfer data length: 8 to 16 bits
Communication modes
Clock synchronous communication mode
4-wire bus communication mode (including bidirectional communication)
- Master or slave device can be selected.
- Continuous transmission and reception of serial data are supported because the
shift, transmit, and receive registers are independent.
I/O pins
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip select I/O pin
Transfer clocks
When the MST bit in the SICR1 register is 0 (slave mode)
External clock (input from the SSCK pin)
When the MST bit in the SICR1 register is 1 (master mode)
Internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4,
output from the SSCK pin)
The clock polarity and phase can be selected.
Receive error detection
Overrun error detection
Indicates an overrun error has occurred during reception and reception is
terminated in error. When the next serial data reception completes while the RDRF
bit in the SISR register is 1 (data present in the SIRDR register), the ORER_AL bit
in the SISR register is set to 1 (overrun error).
Multimaster error detection
Conflict error detection
When starting a serial communication while the MS bit in the SIMR2 register is 1
(4-wire bus communication mode) and the MST bit in the SICR1 register is 1
(master mode), the CE_ADZ bit in the SISR register is set to 1 (conflict error) if the
SCS pin input is low.
When the SCS pin input changes from low to high during transfer while the MS bit
in the SIMR2 register is 1 (4-wire bus communication mode) and the MST bit in the
SICR1 register is 0 (slave mode), the CE_ADZ bit in the SISR register is set to 1.
Interrupt sources
5 (transmit end, transmit data empty, receive data full, overrun error, and conflict
error)
Selectable functions
Data transfer direction
MSB first or LSB first can be selected.
SSCK clock polarity
The level (low or high) when the clock stops can be selected.
SSCK clock phase
The edge for data change and data download can be selected.