R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 423 of 730
Aug 05, 2011
Figure 20.7
Transmit Timing Example in UART Mode
D0
D1
D2
D3
D4
D5
D6
D7
ST
P
Parity
bit
TXD2
CTS2
The above diagram applies under the following conditions:
PRYE bit in U2MR register = 1 (parity enabled)
STPS bit in U2MR register = 0 (one stop bit)
CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
U2IRS bit in U2C1 register = 1 (interrupt request generation when transmission is completed)
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of U2BRG count source (f1, f8, f32, or fC1)
fEXT: Frequency of U2BRG count source (external clock)
n: Value set in U2BRG
Set to 0 by acknowledgment of an interrupt request or by a program
D0
D1
D2
D3
D4
D5
D6
D7
ST
P
ST
D0
TXD2
The above diagram applies under the following conditions:
PRYE bit in U2MR register = 0 (parity disabled)
STPS bit in U2MR register = 1 (two stop bits)
CRD bit in U2C0 register = 1 (CTS/RTS function disabled)
U2IRS bit in U2C1 register = 0 (interrupt request generation when the transmit buffer is empty)
Transfer clock
TC
Set to 0 by acknowledgment of an interrupt request or by a program
TC
Transfer clock
Stop
bit
Data is set in U2TB register
Data transfer from U2TB register to
UART2 transmit register
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
ST
D8
D0
D1
D2
D3
D4
D5
D6
D7
ST
D8
D0
D1
ST
SP SP
Stop
bit
The transfer clock stops once because a high level is applied to CTS2 pin when the stop
bit is verified.
The transfer clock resumes running immediately after a low level is applied to CTS2 pin.
Data is set in U2TB register
SP
Data transfer from U2TB register
to UART2 transmit register
Stop
bit
TE bit in
U2C1 register
TI bit in
U2C1 register
TXEPT bit in
U2C0 register
IR bit in
U2TIC register
TE bit in
U2C1 register
TI bit in
U2C1 register
TXEPT bit in
U2C0 register
IR bit in
U2TIC register
Pulsing stops because TE bit is set to 0
SP
Start bit
SP
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of U2BRG count source (f1, f8, f32, or fC1)
fEXT: Frequency of U2BRG count source (external clock)
n: Value set in U2BRG
(1) Transmit timing example when transfer data is 8 bits long (parity enabled, one stop bit)
(2) Transmit timing example when transfer data is 9 bits long (parity disabled, two stop bits)
Pulsing stops because TE bit is set to 0