R8C/38T-A Group
15. Timer RJ
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 239 of 730
Aug 05, 2011
15.4.3
Pulse Output Mode
In this mode, the counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR
register, and the output levels of pins TRJIO and TRJO are inverted for output each time the timer value
underflows.
In pulse output mode, the count value is decremented by 1 each time the count source is input. If the next count
source is input after the count value reaches 0000h, the set value in the reload register is loaded, and an
underflow occurs, generating an interrupt.
In addition, a pulse can be output from pins TRJIO and TRJO. The output level is inverted each time an
underflow occurs. The pulse output from the TRJIO pin can be stopped by the TOPCR bit in the TRJIOC
register.
Also, the output level can be selected by the TEDGSEL bit in the TRJIOC register.
Figure 15.4
Operation Timing Example in Pulse Output Mode
Note:
1. The TRJIO pin becomes high impedance by output enable control on the port selected as the TRJIO function .
Timer RJ counter
Write 1 to the TSTART bit by a program
Count source
Write 0004h to the TRJ register by a program
Write 0002h to the TRJ register by a program
TSTART bit in
TRJCR register
IR bit in
TRJIC register
TRJ register
TRJIO pin output
enabled
TRJO pin output
TRJIO pin output
TUNDF bit in
TRJCR register
Reload register
0002h
FFFFh
0004h
FFFFh
0004h
0001h 0000h 0002h 0001h 0000h 0002h 0001h 0004h 0003h 0002h 0001h 0000h 0004h 0003h
0002h
When the TEDGSEL bit in the TRJIOC register is set to 0 (output is started at high (initial level is high))
FFFFh
0002h
0000h
0001h
0002h
High-impedance state
(1)
Write 1 to the port I/O control bit (PM bit) selected as the TRJIO function
Acknowledgement of an interrupt request
Set to 0 by a program