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R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 500 of 730
Aug 05, 2011
21.4.2
I2C bus Interface Mode
21.4.2.1
I2C bus Format
When the MS bit in the SIMR2 register is set to 0, I2C bus interface mode is used for communication.
of 8 bits.
Figure 21.18
I2C bus Format and Bus Timing
21.4.2.2
I2C bus Slave Addressing
In the I2C bus format, the first 1 byte immediately after a start condition is specified as a slave address. When
this module operates as a slave device, slave addresses can be programmed using bits SVA0 to SVA6 in the
SIMR2 register. However, this does not apply to the “general call address” and the “start byte” defined in the
I2C bus specification.
General call address (0000_000_0)
Since all the devices are addressed, an acknowledge signal is returned.
Start byte (0000_000_1)
All the devices cannot return any acknowledge signal.
S
R/W
A
DATA
A
A/A
P
1
7
1
n
1
m
(a) I
2C bus format (MS = 0)
Number of transfer bits (n = 1 to 8)
Number of transfer frames (m = 1 or more)
S
R/W
A
DATA
A/A
P
1
7
1
n1
1
m1
(b) I
2C bus format (When start condition is retransmitted, MS = 0)
Upper: Number of transfer bits (n1, n2 = 1 to 8)
Lower: Number of transfer frames (m1, m2 = 1 or more)
SLA
A/A
1
S
1
R/W
A
DATA
7
1
n2
SLA
1
m2
(1) I
2C bus format
(2) I
2C bus timing
Legend:
S
: Start condition
The master device changes the SDA signal from high to low while the SCL signal is held high.
SLA
: Slave address
R/W : Indicates the direction of data transmission/reception. Data is transmitted when:
R/W value is 1: From the slave device to the master device
R/W value is 0: From the master device to the slave device
A
: Acknowledge
The receive device sets the SDA signal to low.
DATA : Transmit/receive data
P
: Stop condition
The master device changes the SDA signal from low to high while the SCL signal is held high.
SDA
SCL
S
SLA
R/W
A
DATA
A
DATA
A
P
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9