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R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 473 of 730
Aug 05, 2011
21.2.9
SI Status Register (SISR)
In the SISR register, the bit functions differ between the SSU and I2C bus functions.
21.2.9.1
SSU Function
Notes:
1. Writing 1 to bits CE_ADZ, ORER_AL, RDRF, TEND, and TDRE has no effect. To set any of these bits to 0, write
0 after reading it as 1.
2. When starting a serial communication while the MS bit in the SIMR2 register is 1 (4-wire bus communication
mode) and the MST bit in the SICR1 register is 1 (master mode), the CE_ADZ bit is set to 1 if the SCS pin input
is low. Refer to 21.3.3.4 SCS Pin Control and Arbitration.
When the SCS pin input changes from low to high during transfer while the MS bit in the SIMR2 register is 1 (4-
wire bus communication mode) and the MST bit in the SICR1 register is 0 (slave mode), the CE_ADZ bit is set to
1.
3. Indicates an overrun error has occurred during reception and reception is terminated in error. If the next serial
data receive operation is completed while the RDRF bit is 1 (data present in the SIRDR register), the ORER_AL
bit is set to 1.
After the ORER_AL bit is set to 1 (overrun error), no reception can be performed while the RDRF bit is 1. Also, no
transmission can be performed while the MST bit is 1 (master mode).
4. The RDRF bit is set to 0 when data is read from the SIRDR register. Do not clear this bit by writing 0 when not in
I2C bus interface mode or when not clearing the RDRF bit after DTC access.
5. Bits TEND and TDRE are set to 0 when data is written to the SITDR register.
6. When the SSU function is used, the TDRE bit is set to 1 when the TE_NAKIE bit in the SIER register is set to 1
(transmission enabled).
Address 000EAh (SISR_0)
Bit
b7
b6b5
b4b3b2b1b0
Symbol
After Reset
00000000
Bit
Symbol
Bit Name
Function
R/W
b0
CE_ADZ
0: No conflict error
R/W
b1
AAS
Reserved
Set to 0.
R/W
b2
ORER_AL Overrun error flag
(1)0: No overrun error
R/W
b3
STOP
Reserved
Set to 0.
R/W
b4
NACKF
R/W
b5
RDRF
Receive data register full flag
(1, 4)0: No data in the SIRDR register
1: Data present in the SIRDR register
R/W
b6
TEND
0: The TDRE bit is 0 when the last bit of transmit
data is transmitted
1: The TDRE bit is 1 when the last bit of transmit
data is transmitted
R/W
b7
TDRE
0: Data is not transferred from registers SITDR to
SISDR
1: Data is transferred from registers SITDR to
SISDR
R/W