R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 513 of 730
Aug 05, 2011
21.4.3.3
Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the SICR1 register is 1 and input when the MST bit is 0.
The receive procedure and operation in receive mode are as follows:
(1) Set the ICE bit in the SICR1 register to 1 (transfer operation enabled). Then, set bits CKS0 to CKS3 in the
SICR1 register and the MST bit (initial setting).
(2) Set the MST bit to 1 while the transfer clock is being output. This will start the output of the receive clock.
(3) When the receive operation is completed, data is transferred from registers SISDR to SIRDR and the
RDRF bit in the SISR register is set to 1. When the MST bit is set to 1, the clock is output continuously
since the next byte of data is enabled for reception. Continuous reception is enabled by reading the SIRDR
register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is 1, an overrun
is detected and the ORER_AL bit in the SISR register is set to 1. At this time, the last receive data is
retained in the SIRDR register.
(4) When the MST bit is 1, set the RCVD bit in the SICR1 register to 1 (next receive operation disabled) to
stop reception before reading the SIRDR register. The SCL signal is held high after the following byte of
data reception is completed.
Figure 21.30
Operation Timing in Receive Mode (Clock Synchronous Serial Mode)
SDA
(input)
SCL
8
7
b7
b1
b0
12
SIRDR register
SISDR register
Program
processing
17
81
b6
b7
b0
b6
b0
RDRF bit in
SISR register
MST bit in
SICR1 register
Data 1
Data 2
(2) Set MST bit to 1
(when transfer clock is output).
(3) Read SIRDR register.
2
TRS bit in
SICR1 register
Data 2
Data 3
Data 1
(3) Read SIRDR register.
0