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R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 306 of 730
Aug 05, 2011
17.3.3
PWM2 Mode
Unlike PWM mode, in PWM2 mode, a waveform is output from the TRCIOB pin at a compare match between
registers TRCGRB and TRCGRC. When the BUFEB bit in the TRCMR register is set to 1 (TRCGRD register
is used as a buffer register for TRCRGB register), the TRCGRD register functions as a buffer register for the
TRCGRB register. The output level is determined by the TOB bit in the TRCCR1 register.
When the TOB bit is 0 (output value is low), a low level is output at a compare match with the TRCGRB
register and a high level is output at a compare match with the TRCGRC register. When the TOB bit is 1 (output
value is high), a high level is output at a compare match with the TRCGRB register and a low level is output at
a compare match with the TRCGRC register.
The value in the TRCGRD register is transferred to the TRCGRB register and the counter is cleared by a
compare match with the TRCGRA register. However, the counter is cleared only when the CCLR bit in the
TRCCR1 register is set to 1 (TRCCNT counter is cleared by input capture/compare match A). Also, when
trigger input is enabled by bits TCEG0 and TCEG1 in the TRCCR2 register in PWM2 mode, the value in the
TRCGRD register is transferred to the TRCGRB register and the counter is cleared by a trigger. The timer I/O
pins that are not used in PWM2 mode can be used only as I/O ports.
Figure 17.12
PWM2 Mode Block Diagram
Table 17.12
Combinations of Pin Functions and General Registers for PWM2 Mode
Pin Name
I/O
Compare Match Register
Buffer Register
TRCIOA
I/O
Port function/TRCTRG input
TRCIOB
O
TRCGRB register
TRCGRD register
TRCGRC register
—
TRCIOC
I/O
Port function
TRCIOD
TRCIOA/TRCTRG
Input
control
TRCIOB
Compare match
Count clearing
Trigger
Output
control
TRCCNT
register
Comparator
TRCGRA
register
TRCGRB
register
TRCGRC
register
TRCGRD
register
Compare match