
R8C/38T-A Group
16. Timer RB2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 265 of 730
Aug 05, 2011
Figure 16.7
Example of 16-Bit Timer Operation in Programmable One-Shot Generation Mode
Count
starts
Count
starts
TOPL bit in
TRBIOC register
TSTART bit in
TRBCR register
Count source
Counter input
TCSTF bit in
TRBCR register
TOSSTF bit in
TRBOCR register
INT0 input
TRBPR register
TRBPR count register
TRBPR/TRBPRE
reload register
load signal
TRBO output pin
Interrupt request
one-shot signal
TRBPRE register
01h
00h
FFh
0: High one-shot pulse output, low output at timer stop
Set to 1 by a program
Synchronized with the peripheral system clock
Changed in synchronization with the peripheral system clock
01h
Higher 8-bit decrement
Lower 8-bit decrement
00FFh
0000h
When registers TRBPR, TRBSC, and TRBPRE
are written while the count is stopped, values are
written to both the reload register and counter
TRBPR/TRBPRE
is reloaded
TRBPR/TRBPRE
is reloaded
Changed simultaneously with
count start and stop
Set to 0 by acknowledgment of an interrupt request
or by a program
The above diagram applies under the following conditions:
TRBPRE register = 01h, TRBPR register = 01h
TCNT16 bit in TRBMR register = 1 (16-bit timer)
TOPL bit = 0 (high one-shot pulse output, low output at timer stop),
TOCNT bit = 0 (waveform output), INOSTG bit = 1 (one-shot trigger to INT0 pin enabled),
INOSEG bit = 1 (rising edge) in TRBIOC register
TRBIE bit in TRBIR register = 1 (timer RB2 interrupt enabled)
01h
Changed simultaneously with
count start and stop
(16-bit decrement) 0101h
00FFh
0000h
(16-bit decrement) 0101h
01h
00h
Higher 8-bit decrement
Lower 8-bit decrement
00h
FFh
FEh
00h
TRBPRE count register
00h
01h
00h
FFh
01h
FEh
FFh