
R8C/38T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 332 of 730
Aug 05, 2011
18.2.2
Timer RE2 Second Data Register (TRESEC) in Real-Time Clock Mode
Notes:
1. Timer RE2 data registers: TRESEC, TREMIN, TREHR, TREWK, TREDY, TREMON, and TREYR
Set the PROTECT bit in the TREPRC register to 1 (write enabled) before rewriting the TRESEC register.
Set values from 00 to 59 by the BCD code.
Read or write to these bits when the BSY bit is 0 (data not being updated).
This bit is set to 1 while data is updated. Read the following registers or bit when this bit is 0 (data not being
updated):
Timer RE2 data registers
(TRESEC, TREMIN, TREHR, TREWK, TREDY, TREMON, and TREYR)
Bits PM and HR24 in the TRECR register
Write to the following registers or bits when the BSY bit is 0 (data not being updated):
Timer RE2 data registers
(TRESEC, TREMIN, TREHR, TREWK, TREDY, TREMON, and TREYR)
Timer RE2 alarm registers (TREAMN, TREAHR, and TREAWK)
Bits PM and HR24
Registers and bits associated with correction
(The AADJE bit in the TRECR register, the AADJM bit in the TRECSR register, and the TREADJ register)
Address 00170h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
After reset by
RTCRST bit in
TRECR register
0
000
0000
Bit
Symbol
Bit Name
Function
Setting Range
R/W
b0
SC00
First digit of second count bits
Count from 0 to 9 every second.
When the digit increments, 1 is
added to the second digit of
seconds.
0 to 9 (BCD code)
R/W
b1
SC01
R/W
b2
SC02
R/W
b3
SC03
R/W
b4
SC10
Second digit of second count bits
When counting from 0 to 5, 60
seconds are counted.
0 to 5 (BCD code)
R/W
b5
SC11
R/W
b6
SC12
R/W
b7
BSY
Timer RE2 busy flag
This bit is set to 1 while timer RE2 data registers
(1) or
the PM bit in the TRECR register is updated.
R