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R8C/38T-A Group
19. Serial Interface (UART0)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 386 of 730
Aug 05, 2011
19.3
Operation
UART0 supports two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O (UART) mode.
19.3.1
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, transmission or reception is performed using a transfer clock.
Notes:
1. When an external clock is selected, the requirements must be met in either of the following states:
The external clock is set to high when the CKPOL bit in the U0C0 register is 0 (transmit data is output at the
falling edge and receive data is input at the rising edge of the transfer clock).
The external clock is set to low when the CKPOL bit is 1 (transmit data is output at the rising edge and receive
data is input at the falling edge of the transfer clock).
2. If an overrun error occurs, the receive data (b0 to b7) in the U0RB register is undefined.
Table 19.4
Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
The CKDIR bit in the U0MR register is 0 (internal clock): fi/(2 (n + 1))
fi = f1, f8, f32, or fC1
n = Value set in the U0BRG register (00h to FFh)
The CKDIR bit in the U0MR register is 1 (external clock): fEXT (input from the CLK pin)
Transmission start
conditions
To start transmission, the following requirements must be met:
(1) The TE bit in the U0C1 register is set to 1 (transmission enabled).
The TI bit in the U0C1 register is set to 0 (data present in the U0TB register).
Reception start
conditions
To start reception, the following requirements must be met:
(1) The RE bit in the U0C1 register is set to 1 (reception enabled).
The TE bit in the U0C1 register is set to 1 (transmission enabled).
The TI bit in the U0C1 register is set to 0 (data present in the U0TB register).
Interrupt request
generation timing
For transmission, one of the following can be selected.
- The U0IRS bit in the U0C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U0TB register to the UART0 transmit register (at
start of transmission).
- The U0IRS bit in the U0C1 register is set to 1 (transmission completed):
When data transmission from the UART0 transmit register is completed.
For reception
When data is transferred from the UART0 receive register to the U0RB register (at
completion of reception).
Error detection
This error occurs if the next data reception is started and the 7th bit is received before
the U0RB register is read.
Selectable functions
CLK polarity selection
The output and input timing of transfer data can be selected to be either the rising or the
falling edge of the transfer clock.
LSB first or MSB first selection
The start bit can be selected to be bit 0 or bit 7 when transmission and reception are
started.
Continuous receive mode selection
Reading the U0RB register enables reception at the same time.