R8C/38T-A Group
6. Resets
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 55 of 730
Aug 05, 2011
6.3.3
Power-On Reset
When the RESET pin is connected to the VCC pin via a resistor and the VCC pin voltage level rises, the power-
on reset is activated and the CPU, SFRs, and I/O ports are initialized. The internal RAM values will be
undefined. In addition, when a capacitor is connected to the RESET pin, ensure that the voltage applied to the
RESET pin is always 0.8 VCC or more.
When the voltage applied to the VCC pin reaches Vdet0 or above, the low-speed on-chip oscillator clock count
starts. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal goes high and the
MCU proceeds to the reset sequence (refer to
Figure 6.2). The low-speed on-chip oscillator clock with no
division is automatically selected as the CPU clock after a reset.
For the states of the SFRs after a reset, refer to 3.2 Special Function Registers (SFRs).
To use the power-on reset, set the LVDAS bit in the OFS register to 0 (voltage monitor 0 reset enabled) and
enable the voltage monitor 0 reset.
Figure 6.5
Power-On Reset Circuit Example and Operation
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to the Voltage
Detection Circuit chapter for details.
2. tw(por) is the time required for a power-on reset to be enabled while the external power VCC is being held
below the valid voltage (0.5 V).
When VCC falls with voltage monitor 0 reset disabled and then turns on, maintain tw(por) for 1 ms or more.
3. To use the power-on reset, enable the voltage monitor 0 reset by setting the LVDAS bit in the OFS register
to 0.
RESET
VCC
4.7 k
(reference)
Vdet0
(1)
0.5 V
Internal reset signal
tw(por)
External power VCC
(Note 2)
1
fLOCO
32