R8C/38T-A Group
10. Power Control
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 116 of 730
Aug 05, 2011
10.3
Standard Operating Mode
Standard operating mode is further divided into four modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and
the peripheral functions. Power consumption control is implemented by controlling the frequency of the CPU
clock. To operate the peripheral functions using a clock other than the peripheral clocks (f1, f2, f4, f8, and f32), the
oscillation of the target clock needs to be stable. The higher the CPU clock frequency, the higher processing power.
The lower the CPU clock frequency, the lower the power consumption. Stopping unnecessary oscillation circuits
will further reduce power consumption.
When the clock sources for the CPU clock are switched, the new clock needs to be oscillating and stable. Allow the
new clock oscillation to stabilize in a program before switching the clocks.
—: Indicates that either 0 or 1 can be set
Table 10.2
Settings and Modes of Clock Associated Bits
Mode
CM4
Register
CM1 Register
CM0
Register
FRA0
Register
Bits CM42 to
CM40
Bits CM17
and CM16
CM14 Bit
CM13 Bit
CM06 Bit
FRA00 Bit
High-speed clock mode
No division
000b
00b
—
1
0
—
Divide-by-2
000b
01b
—
1
0
—
Divide-by-4
000b
10b
—
1
0
—
Divide-by-8
000b
—
1
—
Divide-by-16
000b
11b
—
1
0
—
High-speed on-chip
oscillator mode
No division
101b
00b
—
0
1
Divide-by-2
101b
01b
—
0
1
Divide-by-4
101b
10b
—
0
1
Divide-by-8
101b
—
1
Divide-by-16
101b
11b
—
0
1
Low-speed on-chip
oscillator mode
No division
001b
00b
0
—
0
—
Divide-by-2
001b
01b
0
—
0
—
Divide-by-4
001b
10b
0
—
0
—
Divide-by-8
001b
—
0
—
1
—
Divide-by-16
001b
11b
0
—
0
—
Low-speed clock mode
No division
010b
00b
—
0
—
Divide-by-2
010b
01b
—
0
—
Divide-by-4
010b
10b
—
0
—
Divide-by-8
010b
—
1
—
Divide-by-16
010b
11b
—
0
—