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R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 479 of 730
Aug 05, 2011
21.3.1.3
Association between Data I/O Pins and SS Shift Register
The connection between the data I/O pins and the SISDR register changes according to the combinations of the
MST bit in the SICR1 register and the MS bit in the SIMR2 register. The connection also changes according to
Figure 21.5
Association between Data I/O Pins and SISDR Register
21.3.1.4
Interrupt Requests
The synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Because these interrupt requests are assigned to the
synchronous serial communication unit interrupt vector table, interrupt sources must be determined using the
CEIE_ACKBT, RIE, TEIE, TIE: Bits in SIER register
CE_ADZ, ORER_AL, RDRF, TEND, TDRE: Bits in SISR register
Note:
1. Not generated in clock synchronous communication mode.
If the generation conditions in
Table 21.7 are met, a synchronous serial communication unit interrupt request is
generated. Set each interrupt source to 0 in the synchronous serial communication unit interrupt routine.
Table 21.7
Interrupt Requests of Synchronous Serial Communication Unit
Interrupt Request
Abbreviation
Generation Condition
Transmit data empty
TXI
TIE = 1 and TDRE = 1
Transmit end
TEI
TEIE = 1 and TEND = 1
Receive data full
RXI
RIE = 1 and RDRF = 1
Overrun error
OEI
RIE = 1 and ORER_AL = 1
Conflict error
CEI
CEIE_ACKBT = 1 and CE_ADZ = 1
(1)SISDR register
SSO
SSI
MS = 0 (clock synchronous communication mode)
SISDR register
SSO
SSI
MS = 1 (4-wire bus communication mode), BIDE = 0
(standard mode), and MST = 0 (slave mode)
SISDR register
SSO
SSI
MS = 1 (4-wire bus communication mode), BIDE = 0
(standard mode), and MST = 1 (master mode)
SISDR register
SSO
SSI
MS = 1 (4-wire bus communication mode) and BIDE
= 1 (bidirectional mode)