- 您现在的位置：买卖IC网 > PDF目录11210 > ADUC7061BCPZ32-RL (Analog Devices Inc)IC MCU 16/32BIT 32KB 32LFCSP PDF资料下载
参数资料
| 型号： | ADUC7061BCPZ32-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 105/108页 |
| 文件大小： | 0K |
| 描述： | IC MCU 16/32BIT 32KB 32LFCSP |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) |
| 标准包装： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | POR，PWM，温度传感器，WDT |
| 输入/输出数： | 8 |
| 程序存储器容量： | 32KB（16K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 数据转换器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页当前第105页第106页第107页第108页
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 96 of 108
SERIAL PERIPHERAL INTERFACE
The ADuC706x integrates a complete hardware serial
peripheral interface (SPI) on chip. SPI is an industry standard,
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and simultaneously received, that is,
full duplex up to a maximum bit rate of 5.12 Mbps.
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCLK, and SS.
MISO (MASTER IN, SLAVE OUT) PIN
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, most significant bit first.
MOSI (MASTER OUT, SLAVE IN) PIN
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, most significant bit first.
SCLK (SERIAL CLOCK I/O) PIN
The master serial clock (SCL) synchronizes the data being
transmitted and received through the MOSI SCLK period.
Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
)
1
(
2
SPIDIV
f
UCLK
CLOCK
SERIAL
+
×
=
The maximum speed of the SPI clock is independent of the
clock divider bits.
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mbps.
In both master and slave modes, data transmit on one edge of
the SCLK signal and sample on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
SLAVE SELECT (P0.0/SSE) INPUT PIN
In SPI slave mode, a transfer is initiated by the assertion of
A
SSEE
A
on the P0.0/
A
SSEE
A
pin, which is an active low input signal. The SPI
port then transmits and receives 8-bit data until the transfer is
concluded by deassertion of
A
SSEE
A
. In slave mode,
A
SSEE
A
is always an
input.
In SPI master mode,
A
SSEE
A
is an active low output signal. It asserts
itself automatically at the beginning of a transfer and deasserts
itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
The SPI pins of the ADuC706x device are represented by the
P0[0:3] function of the following pins:
P0.0/
A
SSEE
A
is the slave chip select pin. In slave mode, this pin
is an input and must be driven low by the master. In
master mode, this pin is an output and goes low at the
beginning of a transfer and high at the end of a transfer.
P0.1/SCLK/SCL is the SCLK pin.
P0.2/MISO is the master in, slave out (MISO) pin.
P0.3/MOSI/SDA is the master out, slave in (MOSI) pin.
To configure P0.0 to P0.3 for SPI mode, Bit 0, Bit 4, Bit 8, and
Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the
GP0CON1 must be set to 1. Note that to write to GP0CON1,
the GP0KEY1 register must be set to 0x7 immediately before
writing to GP0CON1. Also, the GP0KEY2 register must be set
to 0x13 immediately after writing to GP0CON1. The following
code example shows this in detail:
GP0CON0 = BIT0 + BIT4 + BIT8 + BIT12;
//Select SPI/I
2C alternative function for P0[0...3]
GP0KEY1 = 0x7;
//Write to GP0KEY1
GP0CON1 &=~ BIT1;
//Select SPI functionality for P0.0 to P0.3
GP0KEY2 = 0x13;
//Write to GP0KEY2
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B2L-IW-F4 | CONVERTER MOD DC/DC 28V 100W |
| ATMEGA8535L-8JU | MCU AVR 8K ISP FLASH MEM 44-PLCC |
| VI-B2L-IW-F3 | CONVERTER MOD DC/DC 28V 100W |
| ATMEGA8535L-8PU | IC AVR MCU 8K 8MHZ 3V 40DIP |
| VI-B2L-IW-F2 | CONVERTER MOD DC/DC 28V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADUC70SMARTLINKRL7 | 制造商:Analog Devices 功能描述: |
| ADUC70TEL | 制造商:Analog Devices 功能描述:FLASH ARM +5-CH 12BIT ADC - Trays |
| ADUC70TEL-RL7 | 制造商:Analog Devices 功能描述: |
| ADUC7120BBCZ | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADUC7120BBCZ-RL | 制造商:Analog Devices 功能描述:- Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。