参数资料
型号: ADUC7061BCPZ32-RL
厂商: Analog Devices Inc
文件页数: 99/108页
文件大小: 0K
描述: IC MCU 16/32BIT 32KB 32LFCSP
产品变化通告: ADuC7060/1 Idd Specification Change 01/Feb/2010
设计资源: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
标准包装: 5,000
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 10MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 8
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 32
电压 - 电源 (Vcc/Vdd): 2.375 V ~ 2.625 V
数据转换器: A/D 5x24b,8x24b,D/A 1x14b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 32-VFQFN 裸露焊盘,CSP
包装: 带卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 90 of 108
I2C Master Receive, I2CMRX, Register
Name:
I2CMRX
Address:
0xFFFF0908
Default value: 0x00
Access:
Read only
Function:
This 8-bit MMR is the I2C master receive
register.
I2C Master Transmit, I2CMTX, Register
Name:
I2CMTX
Address:
0xFFFF090C
Default value: 0x00
Access:
Write only
Function:
This 8-bit MMR is the I2C master transmit
register.
I2C Master Read Count, I2CMCNT0, Register
Name:
I2CMCNT0
Address:
0xFFFF0910
Default value: 0x0000
Access:
Read and write
Function:
This 16-bit MMR holds the required number
of bytes when the master begins a read
sequence from a slave device.
Table 99. I2CMCNT0 MMR Bit Designations
Bit
Name
Description
15:9
Reserved.
8
I2CRECNT
Set this bit if more than 256 bytes are
required from the slave.
Clear this bit when reading 256 bytes or
fewer.
7:0
I2CRCNT
These eight bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required, set
these bits to 0.
I2C Master Current Read Count, I2CMCNT1, Register
Name:
I2CMCNT1
Address:
0xFFFF0914
Default value: 0x00
Access:
Read only
Function:
This 8-bit MMR holds the number of bytes
received so far during a read sequence with a
slave device.
I2C Address 0, I2CADR0, Register
Name:
I2CADR0
Address:
0xFFFF0918
Default value: 0x00
Access:
Read and write
Function:
This 8-bit MMR holds the 7-bit slave address
and the read/write bit when the master begins
communicating with a slave.
Table 100. I2CADR0 MMR in 7-Bit Address Mode
Bit
Name
Description
7:1
I2CADR
These bits contain the 7-bit address of the
required slave device.
0
R/W
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Table 101. I2CADR0 MMR in 10-Bit Address Mode
Bit
Name
Description
7:3
These bits must be set to [11110b] in 10-bit
address mode.
2:1
I2CMADR
These bits contain ADDR[9:8] in 10-bit
addressing mode.
0
R/W
Read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
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