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参数资料
| 型号： | ADUC7061BCPZ32-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/108页 |
| 文件大小： | 0K |
| 描述： | IC MCU 16/32BIT 32KB 32LFCSP |
| 产品变化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 设计资源： | USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) |
| 标准包装： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | POR，PWM，温度传感器，WDT |
| 输入/输出数： | 8 |
| 程序存储器容量： | 32KB（16K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 数据转换器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
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ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 44 of 108
Bit
Name
Description
4:3
ADCLPMCFG[1:0]
ADC power mode configuration.
[00] = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum
electrical performance.
[01] = ADC low power mode.
[10] = ADC normal mode, same as [00].
[11] = ADC low power plus mode (low power mode and PGA off).
2:0
ADCMD[2:0]
ADC operation mode configuration.
[000] = ADC power-down mode. All ADC circuits and the input amplifier are powered down.
[001] = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts at a
frequency equal to fADC. ADCxRDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT.
[010] = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC
enters idle mode when the single shot conversion is complete. A single conversion takes two to three ADC clock
cycles, depending on the chop mode.
[011] = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. The part enters this mode
after calibration.
[100] = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using
an internally generated 0 V. The calibration is carried out at the user-programmed ADC settings; therefore, as
with a normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled
calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective
ADC. The ADC returns to idle mode, and the calibration and conversion ready status bits are set at the end of
an offset calibration cycle.
Note: Always use ADC0 for single-ended self-calibration cycles on the primary ADC. Always use ADC0/ADC1
when self-calibrating for a differential input to the primary ADC.
[101] = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is
performed on all enabled ADCs. A gain calibration is a two-stage process and takes twice the time of an offset
calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC
returns to idle mode and the calibration and conversion ready status bits are set at the end of a gain calibration
cycle. An ADC self-gain calibration should only be carried out on the primary channel ADC.
Note that self-gain calibration works only when the gain = 1; do not use it when the gain > 1.
[110] = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC
channels against an external zero-scale voltage driven at the ADC input pins. To do this, short the channel externally.
[111] = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC
channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated
after a full-scale calibration sequence.
Primary ADC Control Register
Name:
ADC0CON
Address:
0xFFFF050C
Default value:
0x8000
Access:
Read and write
Function:
The primary channel ADC control MMR is a 16-bit register. If the primary ADC is reconfigured via ADC0CON, the
auxiliary ADC is also reset.
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