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参数资料
型号： ADUC7061BCPZ32-RL
厂商： Analog Devices Inc
文件页数： 52/108页
文件大小： 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
产品变化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
设计资源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
标准包装： 5,000
系列： MicroConverter® ADuC7xxx
核心处理器： ARM7
芯体尺寸： 16/32-位
速度： 10MHz
连通性： I²C，SPI，UART/USART
外围设备： POR，PWM，温度传感器，WDT
输入/输出数： 8
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
RAM 容量： 1K x 32
电压 - 电源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
数据转换器： A/D 5x24b，8x24b，D/A 1x14b
振荡器型： 内部
工作温度： -40°C ~ 125°C
封装/外壳： 32-VFQFN 裸露焊盘，CSP
包装： 带卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 48 of 108
Bit
Name
Description
7
NOTCH2
Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
fNOTCH2
= 1.333 × fNOTCH
where fNOTCH is the location of the first notch in the response.
6:0
SF[6:0]
Sinc3 decimation factor (SF).1 The value (SF) written in these bits controls the oversampling (decimation factor) of the
sinc3 filter. The output rate from the sinc3 filter is given by
fADC
= (512,000/([SF + 1] × 64)) Hz2
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, fADC is forced to 60 Hz.
For SF = 127, fADC is forced to 50 Hz.
For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 46.
1
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
2
In low power mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided by 4 (approximately).
Table 46. ADC Conversion Rates and Settling Times
Chop
Enabled
Averaging
Factor
Running
Average
fADC Normal Mode
fADC Low Power Mode
tSETTLING1
No
64
]
1
[
000
,
512
×
+
SF
64
]
1
[
072
,
131
×
+
SF
ADC
f
3
No
Yes
64
]
1
[
000
,
512
×
+
SF
64
]
1
[
072
,
131
×
+
SF
ADC
f
4
No
Yes
No
]
3
[
64
]
1
[
000
,
512
AF
SF
+
×
+
]
3
[
64
]
1
[
072
,
131
AF
SF
+
×
+
ADC
f
1
No
Yes
]
3
[
64
]
1
[
000
,
512
AF
SF
+
×
+
]
3
[
64
]
1
[
072
,
131
AF
SF
+
×
+
ADC
f
2
Yes
N/A
3
]
3
[
64
]
1
[
000
,
512
+
×
+
AF
SF
3
]
3
[
64
]
1
[
072
,
131
+
×
+
AF
SF
ADC
f
2
1
An additional time of approximately 60 s per ADC is required before the first ADC is available.
Table 47. Allowable Combinations of SF and AF
AF Range
SF
0
1 to 7
8 to 63
0 to 31
Yes
32 to 63
Yes
No
64 to 127
Yes
No
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