参数资料
型号: CORE1553BRT-AR
厂商: Microsemi SoC
文件页数: 17/74页
文件大小: 0K
描述: IP MODULE CORE1553 REMOTE TERM
标准包装: 1
系列: *
Core1553BRT v4.0 Handbook
Command Legalization Interface
The core checks the validity of all 1553B command words. In RTL and Obfuscated versions of the core,
the logic may be implemented externally to the core. The command word is provided, and the logic must
generate the command-valid input. The command legalization interface also provides two strobes that
are used to latch the command value to enable it to be used for address mapping and interrupt vector
extension functions ( Table 3-4 ).
Table 3-4 ? Command Legalization Interface
Port Name
USEEXTOK
Type
In
Description
When 0, the core uses its own internal command-valid logic, enabling all legal,
supported mode codes and all subaddresses.
When 1, the core disables its internal logic and uses the external CMDOK input
for command legality.
CMDVAL[11:0]
Out Active
Command
11:
10:
9:5:
4:0:
0: Non-broadcast
0: Receive
Subaddress
Word count / mode code
1: Broadcast
1: Transmit
These outputs are valid throughout the complete 1553B message. They can also
be used to steer data to particular backend devices. In particular, bit 11 allows
non-broadcast and broadcast messages to be differentiated, as required by MIL-
STD-1553B, Notice 2.
CMDSTB
Out Single-clock-cycle pulse that indicates valid command is received on CMDVAL.
CMDOK
In
Command word is okay (active high). The external logic must set this within 3 μs
from the CMDVAL output changing.
CMDOKOUT
ADDRLAT
INTLAT
Out Command word is okay (output). When USEEXTOK = 0, the core puts out its
“internal command word okay” validation signal.
Out CMDVAL address latch enable output (active high). Used to latch CMDVAL
when it is being used for an address mapping function. ADDRLAT should be
connected to the enable of a rising-edge clock flip-flop.
Out CMDVAL interrupt vector latch enable output (active high). Used to latch
CMDVAL when it is being used for an extended interrupt vector function. INTLAT
should be connected to the enable of a rising-edge clock flip-flop.
Revision 3
17
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