参数资料
| 型号： | CORE1553BRT-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 6/74页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE1553 REMOTE TERM |
| 标准包装： | 1 |
| 系列： | * |
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Introduction
The core consists of six main blocks: 1553B encoders, 1553B decoders, the backend interface, a
command decoder, RT controller blocks, and a command legalization block ( Figure 2 ).
Bus A
Encoder
RT Protocol
Controller
Backend
Bus B
Decoder
Command
Decoder
Interface
Memory
2,048×16
Decoder
Command
Legalization
Core1553BRT
Figure 2 ? Core1553BRT RT Block Diagram
In Core1553BRT, a single 1553B encoder is used. This takes each word to be transmitted and serializes
it, after which the signal is Manchester-encoded. The encoder also includes logic to prevent the RT from
transmitting for longer than the allowed period, and loopback fail logic. The loopback logic monitors the
received data and verifies that the core has correctly received every word that it transmits.
The output of the encoder is gated with the bus enable signals to select which busses the RT should use
to transmit.
The core includes two 1553B decoders. A decoder takes the serial Manchester data received from the
bus and extracts the received data words. A decoder requires a 12, 16, 20, or 24 MHz clock to extract the
data and the clock from the serial stream.
The decoder contains a digital PLL that generates a recovery clock used to sample the incoming serial
data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a
command or data word is received and also performs Manchester encoding and parity error checking.
The backend interface for Core1553BRT allows a simple connection to a memory device or direct
connection to other devices, such as analog to digital converters. The access rates to this memory are
slow, with one read or write every 20 μs. At 12 MHz operation, this is one read or write every 240 clock
cycles.
The backend interface can be configured to connect to either synchronous or asynchronous memory
devices. This allows the core to be connected to synchronous logic, memory within the FPGA, or
external asynchronous memory.
The core implements a simple subaddress to the memory address mapping function, allowing the core to
be directly connected to a memory block. The core also supports an address mapping function that
allows the backend memory map to be modified to emulate legacy 1553B remote terminals, therefore
minimizing system and software changes when adopting Core1553BRT. Associated with this function is
the ability to create a user-specific interrupt vector.
The backend interface supports a standard bus request and grant protocol and provides a WAIT input to
allow the core to interface to slow memory devices.
The command decoder and RT controller blocks decode the incoming command words, verifying their
legality. Then, the protocol state machine responds to the command, transmitting or receiving data or
processing a mode code.
Core1553BRT has an internal command legality block that verifies every 1553B command word. A
separate interface is provided that, when enabled, allows the command legality decoder to be
Revision 3
6
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| CORE1553BRT-EBR-AN | 功能描述:IP MOD CORE1553 EBR ENH BIT RATE RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-EBR-AR | 功能描述:IP MOD CORE1553 EBR ENH BIT RATE RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-OM | 功能描述:IP MODULE CORE1553 REMOTE TERM RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-OMFL | 功能描述:IP MODULE CORE1553 BUS/REMOTE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1 |
| CORE1553BRT-RM | 功能描述:IP MODULE CORE1553 REMOTE TERM RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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