参数资料
| 型号： | CORE1553BRT-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 30/74页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE1553 REMOTE TERM |
| 标准包装： | 1 |
| 系列： | * |
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Operation
Transfer Status Words
At the end of every 1553B bus transfer, a transfer status word is written to the RAM in locations 000–01F
for receive operations and 3E0–3FF for transmit operations. The address used is as follows:
?
?
TSW location, RX commands: '000000' and SA
TSW location, TX commands: '011111' and SA
As an example, the TSW address for a transmit command with subaddress 20 would be '01111110100'
If the RT is implemented without a memory-based backend, the writing of the TSW can be disabled. This
simplifies the design of the backend logic that directly controls backend functions.
Table 5-3 ? Transfer Status Word
Bit(s)
15
14
13
Name
USED
OKAY
BUSN
Description
Set to 1 at the end of the transmit or receive command.
Indicates that no errors are detected; i.e., bits 11 to 5 are all 0.
Indicates on which bus the command was received:
0: BUSA 1: BUSB
12
BROADCAST Indicates a broadcast command.
11
10
9
8
7
6
5
LPBKERRB
LPBKERRA
ILLEGAL
CMD
MEMIFERR
MANERR
PARERR
WCNTERR
Indicates that the loopback logic detected an error in the transmitted data for
bus B.
Indicates that the loopback logic detected an error in the transmitted data for
bus A.
The command was illegal. A request to transmit from either an illegal
subaddress or an illegal mode code was received.
Indicates that the DMA memory access failed to complete quickly enough.
Indicates that a Manchester encoding error was detected in the incoming data.
Indicates that a parity error was detected in the incoming data.
Indicates that an incorrect number of words was received.
4:0
COUNT
SA1 to
SA30
Indicates the number of words received or transmitted for that
subaddress. If WCNTERR is 0, '00000' indicates 32 words.
Otherwise, '00000' indicates zero words transferred.
SA0 or
SA31
Indicates which mode code was received or transmitted per the
1553B specification.
Backend Access Times
During normal operation, the backend must allow a memory access to complete within 19.5 μs. When
either the command word or the TSW is written to memory, the backend must be capable of completing
memory accesses in 10 μs.
While the status word is being transmitted, the core must write the command word to memory and fetch
the first data word. Two memory accesses are performed in the 20 μs that the status word takes to
transmit.
At the end of a “broadcast receive” command, Core1553BRT writes the last data word and the TSW
value before the RT decodes the next command. Two memory accesses occur in the 20 μs that the
command word is being decoded.
The core includes a timer that is set to terminate backend memory access at 19.5 μs or 10.0 μs when
either WRTCMD or WRTTSW are active.
Revision 3
30
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| CORE1553BRT-EBR-AN | 功能描述:IP MOD CORE1553 EBR ENH BIT RATE RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-EBR-AR | 功能描述:IP MOD CORE1553 EBR ENH BIT RATE RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-OM | 功能描述:IP MODULE CORE1553 REMOTE TERM RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-OMFL | 功能描述:IP MODULE CORE1553 BUS/REMOTE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1 |
| CORE1553BRT-RM | 功能描述:IP MODULE CORE1553 REMOTE TERM RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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