参数资料
| 型号： | CORE1553BRT-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 43/74页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE1553 REMOTE TERM |
| 标准包装： | 1 |
| 系列： | * |
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Core1553BRT v4.0 Handbook
Table 6-4 ? VHDL Testbench Modules
Entity
Qtbench
QTBEncDec
QBusmon
QRTsystem
QBusTransceiver
QTBBackend
CWLegality
Source Provided
Yes
No
No
Yes
No
No
Yes
Description
The testbench top level. This contains the bus control function
and several remote terminals.
Test block that emulates a bus controller. Transmits 1553B
command and data words and then decodes the status and data
words generated by an RT in response.
1553B bus monitor. Monitors the bus and reports on the bus
traffic.
Hierarchical block with the core plus transceiver, backend, and
command word legality blocks to the core.
Simply takes the six unidirectional signals from the core and
models a transceiver connected to a bus.
Connects to core backend interface and provides the following
functions:
Implements an asynchronous 2k×16 or 8k×16 memory block,
which provides the 32 receive and transmit subaddresses.
Has a built-in address mapping function.
Loops back the receive subaddress locations to the transmit
memory. On a good message received, interrupts the correctly
received words, which are copied from the RX subaddress to the
TX subaddress. If the address mapping function is enabled, the
“synchronize with data” word is copied to the transmit vector
word memory location.
Generates the interrupt acknowledge.
Implements external command validity checking
The testbench uses a command word legality module that disables subaddresses 26 and 27 for transmit
commands. For receive commands, subaddress 25 is disabled, and subaddress 27 is only enabled for
word counts 1 to 9. "External Command Word Legality Example" on page 54 shows the source code for
a command legality module implementing this behavior.
The Core1553B Model Sim ? library (in the mti/verif_rtl directory) contains compiled models for the
complete environment. Design source code of the top-level blocks is provided in the source directory to
enable you to create your own simulation environment using this testbench as a starting point. Examine
the source files for Qtbench and QRTSystem to obtain a full understanding of the core operation.
Qtbench has a top-level generic, CMODE, that you can set to 0 or 1. When 0, the core is configured with
WRTTSW, WRTCMD, and EXTMDATA set to '100'. When 1, these values are set to '011', and the
Revision 3
43
相关PDF资料 |
PDF描述 |
|---|---|
| CORE8051-AR | IP MODULE CORE8051 |
| COREFFT-RM | IP MODULE COREFFT |
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE1553BRT-EBR-AN | 功能描述:IP MOD CORE1553 EBR ENH BIT RATE RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-EBR-AR | 功能描述:IP MOD CORE1553 EBR ENH BIT RATE RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-OM | 功能描述:IP MODULE CORE1553 REMOTE TERM RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BRT-OMFL | 功能描述:IP MODULE CORE1553 BUS/REMOTE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1 |
| CORE1553BRT-RM | 功能描述:IP MODULE CORE1553 REMOTE TERM RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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