参数资料
| 型号： | CORE1553BRT-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 31/74页 |
| 文件大小： | 0K |
| 描述： | IP MODULE CORE1553 REMOTE TERM |
| 标准包装： | 1 |
| 系列： | * |
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Core1553BRT v4.0 Handbook
Data Transfers – Receive
When a “receive data transfer” command is detected, the core will decode each incoming word. At the
end of each word, the core will assert MEMREQn. When MEMGNTn goes LOW, the core will write the
data word to memory and release MEMREQn. This process is repeated until the correct number of words
has been transferred. The core will then transmit its 1553B status word. Finally, the TSW is also written to
memory.
Data Transfers – Transmit
When a “transmit data transfer” command is detected, the core will transmit its status word and assert
MEMREQn. When MEMGNTn goes LOW, the core will read a data word from memory and release
MEMREQn. Once the word is available, the core will transmit the data word. The core will continue to
request data from the memory interface until the required number of words has been transferred. Finally,
the TSW is written to memory.
RT-to-RT Transfer Support
The core supports RT-to-RT transfers. If a transmitting core does not start transferring data within the
required time, the core will detect this and set the WCNTERR bit in the transfer status word.
Mode Codes
When the core receives a mode code, it first checks its command validity. If the command is valid, it is
processed in accordance with the specification. Otherwise, the message error bit will be set in the 1553B
status word. Table 5-4 lists the supported mode codes.
Two mode codes, (1) “transmit a vector word” and (2) “synchronize with data,” require external data.
When EXTMDATA is inactive, the vector word value is set by the VWORD input, and the “synchronize
with data” word is discarded. When EXTMDATA is active, these values are read from and written to
memory. The MEMADDR output will be similar to a single-word data transfer message; bit 10 will reflect
the command word TX bit, and bits 9:5 will be 00h or 1Fh, depending on whether the mode code
subaddress is set to 0 or 31. Bits 4:0 will be zero. This implies the vector word will be read from location
400h or 7E0h, and the “synchronize with data” word is written to location 000h or 3E0h, depending on
whether subaddress 0 or 31 is used.
When both WRTCMD and WRTTSW are active for each message, the command word and TSW value
will be written to the same location; these writes can be distinguished by the MEMOPER output. This
may cause some system problems, but this can be avoided by implementing an external address
mapper function to map these accesses to different addresses.
Table 5-4 ? Supported Mode Codes
T/R
Mode
Data
Core
Broadcast
Bit
Code
Function and Effect
Word Supports
Allowed
1
00000 Dynamic Bus Control
No
No
No
0
The core does not support bus controller functions, so it
will set the Message Error and Dynamic Bus Control
bits in the status word.
1
00001 Synchronize
No
Yes
Yes
1
The core will assert its SYNCNOW output after the
command word has been received.
1
00010 Transmit Status Word
No
Yes
No
2
The core retransmits the last status word.
Revision 3
31
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