参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 12/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Block Description
The RLDRAM II controller comprises the following two blocks:
■
■
Control logic (encrypted)
Datapath (clear text)
The control logic performs the following actions:
■
■
■
Generates initialization sequence using the RLDRAM II initialization
values set in IP Toolbench
Generates write, read, or refresh accesses when requested at the local
interface
Generates datapath control signals that ensure that the write data is
output on the memory rldramii_dq[] (CIO devices) or
rldramii_d[] (SIO devices) bus during the correct clock cycles
The datapath performs the following actions:
■
■
■
Interfaces to common I/O (CIO) or separate I/O (SIO) RLDRAM II
devices
Generates RLDRAM II clocks
Places RLDRAM II commands onto the memory command bus using
one of the following system PLL clocks on either the rising or falling
edge:
●
●
●
System clock
Write clock
Dedicated clock
■
■
Places write data onto the rldramii_dq[] or rldramii_d[] bus
during the correct clock cycles
Captures the read data using dedicated data strobe signal (DQS)
delay circuitry during DQS mode or an external capture clock in non-
DQS mode
Control Logic
The control logic is responsible for controlling transactions at the memory
interface. The control logic accepts read, write, and refresh requests and
executes them immediately as RLDRAM II transactions.
In addition to reads, writes, and refreshes the control logic is also
responsible for controlling initialization of the RLDRAM II devices.
f
For more information on reads, writes, refreshes, and initialization, see
2–2 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
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