参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 58/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Compile the Example Design
Compile the
Example Design
Before the Quartus II software compiles the example design it runs the IP
Toolbench-generated Tcl constraints script,
auto_add_rldramii_constraints.tcl , which calls the
add_constraints_for_ <variation name> .tcl script for each variation in your
design. The add_constraints_for_ <variation name> .tcl script checks for
any previously added constraints, removes them, and then adds
constraints for that variation.
The constraints script analyzes and elaborates your design, to
automatically extract the hierarchy to your variation. To prevent the
constraints script analyzing and elaborating your design, turn on Enable
Hierarchy Control in the wizard, and enter the correct hierarchy path to
your datapath (refer to step 13 on page 3–6 ).
When the constraints script runs, it creates another script,
remove_constraints_for_ <variation name> .tcl , which you can use to
remove the constraints from your design.
To compile the example instance, follow these steps:
1.
2.
Choose Start Compilation (Processing menu), which runs the add
constraints scripts, compiles the example design, and performs
timing analysis.
View the Timing Analyzer to verify your design meets timing.
If the compilation does not reach the frequency requirements, follow
these steps:
1.
2.
3.
4.
5.
6.
7.
8.
Choose Settings (Assignments menu).
Expand Analysis and Synthesis Settings in the category list.
Select Speed in Optimization Technique.
Expand Fitter Settings .
Turn on Optimize Hold Timing and select All Paths .
Turn on Fast-corner timing .
Click OK .
Re-compile the example design by choosing Start Compilation
(Processing menu).
3–14 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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