参数资料
型号: IP-RLDRAMII
厂商: Altera
文件页数: 6/62页
文件大小: 0K
描述: IP RLDRAM II CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: RLDRAM II 控制器
许可证: 初始许可证
Features
Table 1–2 shows the level of support offered by the RLDRAM II
Controller MegaCore function to each Altera device family.
Table 1–2. Device Family Support
Device Family
HardCopy ? II
Stratix ? II
Stratix II GX
Other device families
Preliminary
Full
Full
No support
Support
Features
Common I/O (CIO) and separate I/O (SIO) device support
Memory burst length 2, 4, and 8-beat support
Nonmultiplexed addressing
Datapath generation
Data strobe signal (DQS) and non-DQS capture modes
Automatic constraint generation
Easy-to-use IP Toolbench interface
IP functional simulation models for use in Altera-supported VHDL
and Verilog HDL simulators
Support for OpenCore Plus evaluation
General
Description
The RLDRAM II controller MegaCore function handles the complex
aspects of using RLDRAM II—initializing the memory devices and
translating read and write requests from the local interface into all the
necessary RLDRAM II command signals.
The RLDRAM II controller is optimized for Altera Stratix II devices and
has preliminary support for Stratix II GX and HardCopy II devices. The
advanced features available in these devices allow you to interface
directly to RLDRAM II devices.
Figure 1–1 on page 1–3 shows a system-level diagram including the
example design that the RLDRAM II Controller MegaCore function
creates for you.
1–2 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
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