参数资料
型号: IP-RLDRAMII
厂商: Altera
文件页数: 20/62页
文件大小: 0K
描述: IP RLDRAM II CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: RLDRAM II 控制器
许可证: 初始许可证
Block Description
rldramii_dq[8:0] is captured by the delayed
rldramii_qk[0]
rldramii_dq[17:9] is captured by the delayed
rldramii_qk[1]
rldramii_dq[26:18] is captured by the delayed
rldramii_qk[2]
rldramii_dq[35:27] is captured by the delayed
rldramii_qk[3]
QVLD is always captured by the delayed version of
rldramii_qk[0] for the associated RLDRAM II device. In
Figure 2–6 there are four rldramii_qk[] signals. Only
rldramii_qk[0] per RLDRAM II device captures the associated
QVLD signal:
rldramii_qvld[0] is captured by the delayed
rldramii_qk[0]
rldramii_qvld[1] is captured by the delayed
rldramii_qk[2]
After the capture registers all captured read data is clocked off the
undelayed rldramii_qk[] signal that captures the QVLD signal
for a particular RLDRAM II device:
All RLDRAM II 0 captured data is clocked off the undelayed
rldramii_qk[0]
All RLDRAM II 1 captured data is clocked off the undelayed
rldramii_qk[2]
Only one capture_clk[] per attached RLDRAM II device is
output from the datapath:
RLDRAM II 0 capture data is associated with
capture_clk[0] , which is the delayed rldramii_qk[0]
RLDRAM II 1 capture data is associated with
capture_clk[1] , which is the delayed rldramii_qk[2]
Read Data Capture Clock Association
Figure 2–7 shows the read data and data strobes at the memory interface
for the example datapath in Figure 2–6 . Figure 2–8 shows how the
capture_clk[] associates with the captured read data,
control_rdata[] at the datapath interface.
2–10 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
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