参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 24/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Device-Level Configuration
Figure 2–9. PLL Configuration
FPGA Device
Enhanced PLL
non_dqs_capture_clk
Optional
Fed-Back Clock
PLL (Note 1)
RLDRAM II Controller
rldramii_qk
clock_source
C0
C1
clk
write_clk
altddio
rldramii_clk_n
rldramii_clk
altddio
Address &
RLDRAM II
C2
addr_cmd_clk
(Note 2)
Command
Registers
rldramii_a_0[]
rldramii_ba_0[]
rldramii_cs_n_0
rldramii_ref_n_0
rldramii_we_n_0
C3
Stratix II DLL
(1)
(2)
Non-DQS mode only.
You can connect the addr_cmd_clk RLDRAM II controller input to clk , write_clk or to the dedicated PLL
output C2.
Example Design
IP Toolbench creates an example design that shows you how to
instantiate and connect up the RLDRAM II controller to an example
driver. The example design is a working system that can be compiled and
used for both static timing checks and board tests. It also instantiates an
example PLL that generates all the required clocks for the controller. In
DQS mode, a DLL is instantiated that controls the DQS capture delay
phase. In non-DQS mode, the example design instantiates a fedback PLL.
The output of the fedback PLL is a phase-shifted rldramii_qk[] data
strobe, which captures the read data.
The example driver is a self-checking test generator for the RLDRAM II
controller. It uses a state machine to write data patterns to all memory
banks. It then reads back the data and checks that the data matches. If any
read data fails the comparison, the pnf_per_byte output transitions
low for one cycle and the pnf_persist permanent output transitions
low and stays low.
2–14 MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
Altera Corporation
November 2009
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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