参数资料
| 型号： | IP-RLDRAMII |
| 厂商： | Altera |
| 文件页数： | 35/62页 |
| 文件大小： | 0K |
| 描述： | IP RLDRAM II CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | RLDRAM II 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Table 2–3. System Signals (Part 3 of 3)
Name
reset_read_clk_n[]
Width
(Bits)
DQS mode:
the number of
RLDRAM II devices
attached to the memory
interface
Direction
Input
Description
Reset input for logic on the capture clock
domain. In DQS mode, the capture clock
domain is capture_clk[] ; in non-DQS
mode, it is non_dqs_capture_clk . In
DQS mode, each
reset_read_clk_n[] is associated
Non-DQS mode:
1
with the corresponding capture_clk[]
clock domain. The
reset_read_clk_n[] can be asserted
asynchronously but must be deasserted
synchronous to the rising edge of the
capture clock.
capture_clk[]
The number of
RLDRAM II devices
attached to memory
interface
Output
Undelayed DQS clock used by capture
circuitry to capture RLDRAM II read data.
There is one capture_clk[] per
attached RLDRAM II device. DQS mode
only.
Table 2–4. Local Interface Signals (Part 1 of 2)
Name
local_addr[]
Width
(Bits)
Device dependant
Direction
Input
Description
RLDRAM II address. IP Toolbench refers to the
memory.dat file and selects the address width
appropriate to the device.
local_bank_addr[]
local_dm[]
3
The number of
RLDRAM II devices
attached to the
–
Input
RLDRAM II bank address.
Optional local data mask (DM). Twice the width of
the memory rldramii_dm[] bus. When all
high, all writes are masked.
memory interface ×
2
local_read_req
local_refresh_req
1
1
Input
Input
Read request signal.
User controlled refresh request. This allows
complete control over when refreshes are issued
to the memory. The refresh is issued to the bank
address on local_bank_addr[] .
Altera Corporation
November 2009
MegaCore Version 9.1 2–25
RLDRAM II Controller MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
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| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
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| IPR-NCO | 功能描述:开发软件 NCO Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-NIOS | 功能描述:开发软件 Nios II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPROBER 520 | 制造商:TTi-Thurlby Thandar Instruments 功能描述:Bulk 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, POSITIONAL, ON PCB TRACK 制造商:Aim & Thurlby Thandar Instruments 功能描述:PROBE, CURRENT, 5MHZ, 2M; Test Probe Ratio:-; Connector Type A:-; Connector Type B:-; Lead Length:2m; Bandwidth:5MHz; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: NA |
| IPR-PCI/MT32 | 功能描述:开发软件 PCI 32b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-PCI/MT64 | 功能描述:开发软件 PCI 64b MasterTarget MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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