参数资料
型号: IP-RLDRAMII
厂商: Altera
文件页数: 7/62页
文件大小: 0K
描述: IP RLDRAM II CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: RLDRAM II 控制器
许可证: 初始许可证
About This MegaCore Function
Figure 1–1. RLDRAM II Controller System-Level Diagram
Example Design
Local
Pass
or Fail
Clock
Example
Driver
System
PLL
Interface
Control Logic
(Encrypted)
RLDRAM II
Interface
RLDRAM II
Datapath
(Clear Text)
DLL
Fedback
Note to Figure 1–1 :
Clock
PLL (1)
RLDRAM II Controller
(1)
Non-DQS mode only.
IP Toolbench generates the following items:
A testbench, which instantiates the example design
A synthesizable example design which instantiates the following
modules:
RLDRAM II controller:
?
?
Encrypted control logic, which takes transaction requests
from the local interface and issues writes, reads, and
refreshes to the memory interface
A clear-text datapath
Altera Corporation
November 2009
Example driver—generates write, read and refresh requests and
outputs a pass_fail signal to indicate that the tests are
passing or failing
System phase-locked loop (PLL)—generates the RLDRAM II
controller clocks
Delay locked loop (DLL)—instantiated in DQS mode and
generates the DQS delay control signal for the dedicated DQS
delay circuitry
MegaCore Version 9.1 1–3
RLDRAM II Controller MegaCore Function User Guide
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